Commit 76b1ca47 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src, test: Resolve synthesis complaints!

parent d8a5af39
Pipeline #13713 canceled with stages
...@@ -354,7 +354,6 @@ architecture rtl of can_core is ...@@ -354,7 +354,6 @@ architecture rtl of can_core is
signal crc_enable : std_logic; signal crc_enable : std_logic;
signal crc_spec_enable : std_logic; signal crc_spec_enable : std_logic;
signal crc_calc_from_rx : std_logic; signal crc_calc_from_rx : std_logic;
signal crc_src : std_logic_vector(1 downto 0);
signal crc_15 : std_logic_vector(14 downto 0); signal crc_15 : std_logic_vector(14 downto 0);
signal crc_17 : std_logic_vector(16 downto 0); signal crc_17 : std_logic_vector(16 downto 0);
signal crc_21 : std_logic_vector(20 downto 0); signal crc_21 : std_logic_vector(20 downto 0);
...@@ -567,7 +566,6 @@ begin ...@@ -567,7 +566,6 @@ begin
crc_spec_enable => crc_spec_enable, -- OUT crc_spec_enable => crc_spec_enable, -- OUT
crc_calc_from_rx => crc_calc_from_rx, -- OUT crc_calc_from_rx => crc_calc_from_rx, -- OUT
load_init_vect => load_init_vect, -- OUT load_init_vect => load_init_vect, -- OUT
crc_src => crc_src, -- OUT
crc_15 => crc_15, -- IN crc_15 => crc_15, -- IN
crc_17 => crc_17, -- IN crc_17 => crc_17, -- IN
crc_21 => crc_21, -- IN crc_21 => crc_21, -- IN
...@@ -894,7 +892,6 @@ begin ...@@ -894,7 +892,6 @@ begin
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
stat_bus(511 downto 385) <= (OTHERS => '0'); stat_bus(511 downto 385) <= (OTHERS => '0');
stat_bus(299 downto 297) <= (OTHERS => '0'); stat_bus(299 downto 297) <= (OTHERS => '0');
stat_bus(187) <= '0';
stat_bus(98 downto 90) <= (OTHERS => '0'); stat_bus(98 downto 90) <= (OTHERS => '0');
stat_bus(60 downto 32) <= (OTHERS => '0'); stat_bus(60 downto 32) <= (OTHERS => '0');
stat_bus(113) <= '0'; stat_bus(113) <= '0';
......
...@@ -354,9 +354,6 @@ entity protocol_control is ...@@ -354,9 +354,6 @@ entity protocol_control is
-- Load CRC Initialization vector -- Load CRC Initialization vector
load_init_vect :out std_logic; load_init_vect :out std_logic;
-- CRC Source to be used (CRC 15, CRC 17, CRC 21)
crc_src :out std_logic_vector(1 downto 0);
-- Calculated CRC 15 -- Calculated CRC 15
crc_15 :in std_logic_vector(14 downto 0); crc_15 :in std_logic_vector(14 downto 0);
...@@ -586,7 +583,7 @@ architecture rtl of protocol_control is ...@@ -586,7 +583,7 @@ architecture rtl of protocol_control is
signal crc_clear_match_flag : std_logic; signal crc_clear_match_flag : std_logic;
-- CRC Source (CRC15, CRC17, CRC21) -- CRC Source (CRC15, CRC17, CRC21)
signal crc_src_i : std_logic_vector(1 downto 0); signal crc_src : std_logic_vector(1 downto 0);
-- Error position field (for Error capture) -- Error position field (for Error capture)
signal err_pos : std_logic_vector(4 downto 0); signal err_pos : std_logic_vector(4 downto 0);
...@@ -769,7 +766,7 @@ begin ...@@ -769,7 +766,7 @@ begin
crc_match => crc_match, -- IN crc_match => crc_match, -- IN
crc_err => crc_err_i, -- OUT crc_err => crc_err_i, -- OUT
crc_clear_match_flag => crc_clear_match_flag, -- OUT crc_clear_match_flag => crc_clear_match_flag, -- OUT
crc_src => crc_src_i, -- OUT crc_src => crc_src, -- OUT
err_pos => err_pos, -- OUT err_pos => err_pos, -- OUT
is_arbitration => is_arbitration_i, -- OUT is_arbitration => is_arbitration_i, -- OUT
...@@ -934,7 +931,7 @@ begin ...@@ -934,7 +931,7 @@ begin
err_pos => err_pos, -- IN err_pos => err_pos, -- IN
crc_check => crc_check, -- IN crc_check => crc_check, -- IN
crc_clear_match_flag => crc_clear_match_flag, -- IN crc_clear_match_flag => crc_clear_match_flag, -- IN
crc_src => crc_src_i, -- IN crc_src => crc_src, -- IN
drv_fd_type => drv_fd_type, -- IN drv_fd_type => drv_fd_type, -- IN
is_arbitration => is_arbitration_i, -- IN is_arbitration => is_arbitration_i, -- IN
is_transmitter => is_transmitter, -- IN is_transmitter => is_transmitter, -- IN
...@@ -969,7 +966,7 @@ begin ...@@ -969,7 +966,7 @@ begin
tx_load_crc => tx_load_crc, -- IN tx_load_crc => tx_load_crc, -- IN
tx_shift_ena => tx_shift_ena, -- IN tx_shift_ena => tx_shift_ena, -- IN
tx_dominant => tx_dominant, -- IN tx_dominant => tx_dominant, -- IN
crc_src => crc_src_i, -- IN crc_src => crc_src, -- IN
-- CAN CRC Interface -- CAN CRC Interface
crc_15 => crc_15, -- IN crc_15 => crc_15, -- IN
...@@ -1044,7 +1041,6 @@ begin ...@@ -1044,7 +1041,6 @@ begin
crc_err <= crc_err_i; crc_err <= crc_err_i;
is_arbitration <= is_arbitration_i; is_arbitration <= is_arbitration_i;
fixed_stuff <= fixed_stuff_i; fixed_stuff <= fixed_stuff_i;
crc_src <= crc_src_i;
arbitration_lost <= arbitration_lost_i; arbitration_lost <= arbitration_lost_i;
-- <RELEASE_OFF> -- <RELEASE_OFF>
......
...@@ -2199,9 +2199,6 @@ package can_components is ...@@ -2199,9 +2199,6 @@ package can_components is
-- Load CRC Initialization vector -- Load CRC Initialization vector
load_init_vect :out std_logic; load_init_vect :out std_logic;
-- CRC Source to be used (CRC 15, CRC 17, CRC 21)
crc_src :out std_logic_vector(1 downto 0);
-- Calculated CRC 15 -- Calculated CRC 15
crc_15 :in std_logic_vector(14 downto 0); crc_15 :in std_logic_vector(14 downto 0);
...@@ -3740,12 +3737,6 @@ package can_components is ...@@ -3740,12 +3737,6 @@ package can_components is
-- Start of Frame pulse -- Start of Frame pulse
sof_pulse :in std_logic; sof_pulse :in std_logic;
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving bus
drv_bus :in std_logic_vector(1023 downto 0);
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- FSM outputs -- FSM outputs
----------------------------------------------------------------------- -----------------------------------------------------------------------
......
...@@ -337,10 +337,10 @@ begin ...@@ -337,10 +337,10 @@ begin
txtb_port_a_cs_gen : for i in 0 to G_TXT_BUFFER_COUNT - 1 generate txtb_port_a_cs_gen : for i in 0 to G_TXT_BUFFER_COUNT - 1 generate
type tx_buff_addr_type is array (0 to G_TXT_BUFFER_COUNT - 1) of type tx_buff_addr_type is array (0 to G_TXT_BUFFER_COUNT - 1) of
std_logic_vector(3 downto 0); std_logic_vector(3 downto 0);
signal buf_addr : tx_buff_addr_type := (TX_BUFFER_1_BLOCK, constant buf_addr : tx_buff_addr_type := (TX_BUFFER_1_BLOCK,
TX_BUFFER_2_BLOCK, TX_BUFFER_2_BLOCK,
TX_BUFFER_3_BLOCK, TX_BUFFER_3_BLOCK,
TX_BUFFER_4_BLOCK); TX_BUFFER_4_BLOCK);
begin begin
txtb_port_a_cs(i) <= '1' when ((adress(11 downto 8) = buf_addr(i)) and txtb_port_a_cs(i) <= '1' when ((adress(11 downto 8) = buf_addr(i)) and
scs = '1' and swr = '1') scs = '1' and swr = '1')
...@@ -964,6 +964,7 @@ begin ...@@ -964,6 +964,7 @@ begin
align_reg_to_wrd(REC_VAL_H, length) downto align_reg_to_wrd(REC_VAL_H, length) downto
align_reg_to_wrd(REC_VAL_L, length)) <= align_reg_to_wrd(REC_VAL_L, length)) <=
stat_bus(STAT_RX_COUNTER_HIGH downto STAT_RX_COUNTER_LOW); stat_bus(STAT_RX_COUNTER_HIGH downto STAT_RX_COUNTER_LOW);
Control_registers_in.rec(15 downto 9) <= (OTHERS => '0');
end block rec_reg_block; end block rec_reg_block;
...@@ -977,6 +978,7 @@ begin ...@@ -977,6 +978,7 @@ begin
align_reg_to_wrd(TEC_VAL_H, length) downto align_reg_to_wrd(TEC_VAL_H, length) downto
align_reg_to_wrd(TEC_VAL_L, length)) <= align_reg_to_wrd(TEC_VAL_L, length)) <=
stat_bus(STAT_TX_COUNTER_HIGH downto STAT_TX_COUNTER_LOW); stat_bus(STAT_TX_COUNTER_HIGH downto STAT_TX_COUNTER_LOW);
Control_registers_in.tec(15 downto 9) <= (OTHERS => '0');
end block tec_reg_block; end block tec_reg_block;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -1245,7 +1247,7 @@ begin ...@@ -1245,7 +1247,7 @@ begin
align_reg_to_wrd(TRV_DELAY_VALUE_H, length) downto align_reg_to_wrd(TRV_DELAY_VALUE_H, length) downto
align_reg_to_wrd(TRV_DELAY_VALUE_L, length)) <= align_reg_to_wrd(TRV_DELAY_VALUE_L, length)) <=
trv_delay; trv_delay;
Control_registers_in.trv_delay(15 downto 7) <= (others => '0');
end block trv_delay_block; end block trv_delay_block;
......
...@@ -437,7 +437,6 @@ begin ...@@ -437,7 +437,6 @@ begin
rec_valid_f => rec_valid_f, -- IN rec_valid_f => rec_valid_f, -- IN
rec_abort_f => rec_abort_f, -- IN rec_abort_f => rec_abort_f, -- IN
sof_pulse => sof_pulse, -- IN sof_pulse => sof_pulse, -- IN
drv_bus => drv_bus, -- IN
write_raw_intent => write_raw_intent, -- OUT write_raw_intent => write_raw_intent, -- OUT
write_ts => write_ts, -- OUT write_ts => write_ts, -- OUT
......
...@@ -97,12 +97,6 @@ entity rx_buffer_fsm is ...@@ -97,12 +97,6 @@ entity rx_buffer_fsm is
-- Start of Frame pulse -- Start of Frame pulse
sof_pulse :in std_logic; sof_pulse :in std_logic;
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving bus
drv_bus :in std_logic_vector(1023 downto 0);
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- FSM outputs -- FSM outputs
----------------------------------------------------------------------- -----------------------------------------------------------------------
...@@ -132,12 +126,6 @@ end entity; ...@@ -132,12 +126,6 @@ end entity;
architecture rtl of rx_buffer_fsm is architecture rtl of rx_buffer_fsm is
----------------------------------------------------------------------------
-- Driving bus signal aliases
----------------------------------------------------------------------------
-- Receive Timestamp options
signal drv_rtsopt : std_logic;
-- RX Buffer FSM -- RX Buffer FSM
signal curr_state : t_rx_buf_state; signal curr_state : t_rx_buf_state;
signal next_state : t_rx_buf_state; signal next_state : t_rx_buf_state;
...@@ -145,20 +133,18 @@ architecture rtl of rx_buffer_fsm is ...@@ -145,20 +133,18 @@ architecture rtl of rx_buffer_fsm is
-- Clock enable for state register -- Clock enable for state register
signal rx_fsm_ce : std_logic; signal rx_fsm_ce : std_logic;
-- <RELEASE_OFF>
-- Joined commands (for assertions only) -- Joined commands (for assertions only)
signal cmd_join : std_logic_vector(3 downto 0); signal cmd_join : std_logic_vector(3 downto 0);
begin -- <RELEASE_ON>
---------------------------------------------------------------------------- begin
-- Driving bus aliases
----------------------------------------------------------------------------
drv_rtsopt <= drv_bus(DRV_RTSOPT_INDEX);
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Next State process -- Next State process
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
next_state_proc : process(curr_state, store_metadata_f, rec_abort_f, next_state_proc : process(curr_state, store_metadata_f, rec_abort_f,
rec_valid_f, drv_rtsopt) rec_valid_f)
begin begin
next_state <= curr_state; next_state <= curr_state;
...@@ -314,15 +300,15 @@ begin ...@@ -314,15 +300,15 @@ begin
-- Clock enable for State reg -- Clock enable for State reg
rx_fsm_ce <= '1' when (next_state /= curr_state) else rx_fsm_ce <= '1' when (next_state /= curr_state) else
'0'; '0';
-- Joined commands, for assertions only
cmd_join <= store_metadata_f & store_data_f & rec_valid_f & rec_abort_f;
-- <RELEASE_OFF> -- <RELEASE_OFF>
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- Assertions -- Assertions
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys); -- psl default clock is rising_edge(clk_sys);
-- Joined commands, for assertions only
cmd_join <= store_metadata_f & store_data_f & rec_valid_f & rec_abort_f;
-- psl store_metadata_in_idle_asrt : assert never -- psl store_metadata_in_idle_asrt : assert never
-- (store_metadata_f = '1' and (curr_state /= s_rxb_idle)) -- (store_metadata_f = '1' and (curr_state /= s_rxb_idle))
......
...@@ -235,7 +235,6 @@ architecture Protocol_Control_unit_test of CAN_test is ...@@ -235,7 +235,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- CRC Interface -- CRC Interface
signal crc_enable_1 : std_logic; signal crc_enable_1 : std_logic;
signal crc_spec_enable_1 : std_logic; signal crc_spec_enable_1 : std_logic;
signal crc_src_1 : std_logic_vector(1 downto 0);
-- Control signals -- Control signals
signal sp_control_1 : std_logic_vector(1 downto 0); signal sp_control_1 : std_logic_vector(1 downto 0);
...@@ -346,7 +345,6 @@ architecture Protocol_Control_unit_test of CAN_test is ...@@ -346,7 +345,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- CRC Interface -- CRC Interface
signal crc_enable_2 : std_logic; signal crc_enable_2 : std_logic;
signal crc_spec_enable_2 : std_logic; signal crc_spec_enable_2 : std_logic;
signal crc_src_2 : std_logic_vector(1 downto 0);
-- Control signals -- Control signals
signal sp_control_2 : std_logic_vector(1 downto 0); signal sp_control_2 : std_logic_vector(1 downto 0);
...@@ -746,7 +744,6 @@ begin ...@@ -746,7 +744,6 @@ begin
-- CRC Interface -- CRC Interface
crc_enable => crc_enable_1, crc_enable => crc_enable_1,
crc_spec_enable => crc_spec_enable_1, crc_spec_enable => crc_spec_enable_1,
crc_src => crc_src_1,
crc_15 => crc_15, crc_15 => crc_15,
crc_17 => crc_17, crc_17 => crc_17,
crc_21 => crc_21, crc_21 => crc_21,
...@@ -869,7 +866,6 @@ begin ...@@ -869,7 +866,6 @@ begin
-- CRC Interface -- CRC Interface
crc_enable => crc_enable_2, crc_enable => crc_enable_2,
crc_spec_enable => crc_spec_enable_2, crc_spec_enable => crc_spec_enable_2,
crc_src => crc_src_2,
crc_15 => crc_15, crc_15 => crc_15,
crc_17 => crc_17, crc_17 => crc_17,
crc_21 => crc_21, crc_21 => crc_21,
......
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