Commit 754c14d0 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: New prescaler bug-fixes.

parent 1d1d74a9
......@@ -841,7 +841,8 @@ package can_components is
signal tq_edge_nbt : in std_logic;
signal tq_edge_dbt : in std_logic;
signal segm_end : out std_logic;
signal h_sync_valid : out std_logic
signal h_sync_valid : out std_logic;
signal bt_ctr_clear : out std_logic
);
end component;
......
......@@ -42,6 +42,14 @@
--------------------------------------------------------------------------------
-- Purpose:
-- Bit time FSM.
--
-- Bit Time FSM has three states:
-- 1. Reset
-- 2. TSEG1
-- 3. TSEG2
--
-- Output of Bit time FSM are SYNC and SAMPLE requests for SYNC and SAMPLE
-- trigger generator.
--------------------------------------------------------------------------------
-- Revision History:
-- 15.02.2019 Created file
......@@ -162,6 +170,10 @@ begin
case current_state is
when reset =>
if (drv_ena = CTU_CAN_ENABLED) then
sync_req <= '1';
end if;
when tseg1 =>
is_tseg1 <= '1';
if (segm_end = '1') then
......
......@@ -44,10 +44,10 @@
-- Information processing Time checker.
--
-- Checks length of Information processing time after Sample point between
-- PH1 and PH2. Functions like a half-handshake. When 'ipt_req' comes, interna
-- shift register is preloaded. This shift register shifts each clock cycle
-- and after input value was shifted till the very end, 'ipt_gnt' is set
-- high and remains high till the next 'ipt_req'.
-- PH1 and PH2. Functions like a half-handshake. When 'ipt_req' comes,
-- internal shift register is preloaded. This shift register shifts each
-- clock cycle and after input value was shifted till the very end, 'ipt_gnt'
-- is set high and remains high till the next 'ipt_req'.
--------------------------------------------------------------------------------
-- Revision History:
-- 03.02.2019 Created file
......
......@@ -103,56 +103,56 @@ entity prescaler is
sample_trigger_count : natural range 2 to 8 := 3
);
port(
------------------------
--Clock and async reset-
------------------------
---------------------------------------------------------------------------
-- Clock and async reset
---------------------------------------------------------------------------
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async reset
-----------------------
--Bus synch Interface--
-----------------------
---------------------------------------------------------------------------
-- Bus synch Interface
---------------------------------------------------------------------------
signal sync_edge :in std_logic; --Edge for synchronisation
signal OP_State :in oper_mode_type; --Protocol control state
--Driving Bus
signal drv_bus :in std_logic_vector(1023 downto 0);
-------------------------------------
--Generated clock - Nominal bit time-
-------------------------------------
---------------------------------------------------------------------------
-- Generated clock - Nominal bit time
---------------------------------------------------------------------------
--Time quantum clock - Nominal bit time
signal clk_tq_nbt :out std_logic;
--Time quantum - Data bit time
signal clk_tq_dbt :out std_logic;
--------------------------------------
--Sample signals and delayed signals
--------------------------------------
---------------------------------------------------------------------------
-- Sample signals and delayed signals
---------------------------------------------------------------------------
signal sample_nbt :out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sample_dbt :out std_logic_vector(sample_trigger_count - 1 downto 0);
--------------------------------------
---------------------------------------------------------------------------
-- Sync Signals
--------------------------------------
---------------------------------------------------------------------------
signal sync_nbt :out std_logic_vector(sync_trigger_count - 1 downto 0);
signal sync_dbt :out std_logic_vector(sync_trigger_count - 1 downto 0);
signal bt_FSM_out :out bit_time_type;
--What is actual node transmitting on the bus
-- What is actual node transmitting on the bus
signal data_tx :in std_logic;
--Validated hard synchronisation edge to start Protocol control FSM
--Note: Sync edge from busSync.vhd cant be used! If it comes during sample
-- nbt, sequence it causes errors! It needs to be strictly before or
-- strictly after this sequence!!!
-- Validated hard synchronisation edge to start Protocol control FSM
-- Note: Sync edge from busSync.vhd cant be used! If it comes during sample
-- nbt, sequence it causes errors! It needs to be strictly before or
-- strictly after this sequence!!!
signal hard_sync_edge_valid :out std_logic;
-------------------------
--Clock source control --
-------------------------
---------------------------------------------------------------------------
-- Bit timing and Synchronisation control
---------------------------------------------------------------------------
signal sp_control :in std_logic_vector(1 downto 0);
signal sync_control :in std_logic_vector(1 downto 0)
);
......@@ -192,14 +192,11 @@ architecture rtl of prescaler is
signal tseg2_dbt : std_logic_vector(tseg2_dbt_width - 1 downto 0);
signal brp_dbt : std_logic_vector(tq_dbt_width - 1 downto 0);
signal sjw_dbt : std_logic_vector(sjw_dbt_width - 1 downto 0);
-- No positive resynchronisation.
-- TODO: Move this to operation control FSM!
signal no_pos_resync : std_logic;
---------------------------------------------------------------------------
-- Internal signals
---------------------------------------------------------------------------
-- End of segment is detected (by segment end detector)
signal segment_end : std_logic;
......@@ -250,10 +247,21 @@ architecture rtl of prescaler is
-- Signal that expected semgent length should be loaded after restart!
signal start_edge : std_logic;
-- Bit time counter clear
signal bt_ctr_clear : std_logic;
begin
drv_ena <= drv_bus(DRV_ENA_INDEX);
---------------------------------------------------------------------------
-- No positive resynchronisation detection.
-- TODO: This will be moved to Operation control!
---------------------------------------------------------------------------
no_pos_resync <= '1' when (OP_State = transciever and data_tx = DOMINANT)
else
'0';
---------------------------------------------------------------------------
-- Bit time config capture
......@@ -366,8 +374,8 @@ begin
clk_sys => clk_sys,
res_n => res_n,
prescaler => brp_nbt,
tq_reset => segment_end,
bt_reset => segment_end,
tq_reset => bt_ctr_clear,
bt_reset => bt_ctr_clear,
drv_ena => drv_ena,
tq_edge => tq_edge_nbt,
bt_counter => bt_counter_nbt
......@@ -416,8 +424,8 @@ begin
clk_sys => clk_sys,
res_n => res_n,
prescaler => brp_dbt,
tq_reset => segment_end,
bt_reset => segment_end,
tq_reset => bt_ctr_clear,
bt_reset => bt_ctr_clear,
drv_ena => drv_ena,
tq_edge => tq_edge_dbt,
bt_counter => bt_counter_dbt
......@@ -443,7 +451,8 @@ begin
tq_edge_nbt => tq_edge_nbt,
tq_edge_dbt => tq_edge_dbt,
segm_end => segment_end,
h_sync_valid => h_sync_valid
h_sync_valid => h_sync_valid,
bt_ctr_clear => bt_ctr_clear
);
......@@ -493,6 +502,9 @@ begin
---------------------------------------------------------------------------
hard_sync_edge_valid <= h_sync_valid;
clk_tq_nbt <= tq_edge_nbt;
clk_tq_dbt <= tq_edge_dbt;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Assertions
......
......@@ -307,6 +307,13 @@ architecture rtl of resynchronisation is
-- Regular exit of Bit segment
signal exit_segm_regular : std_logic;
-- Regular exit for TSEG1, TSEG2
signal exit_segm_regular_tseg1 : std_logic;
signal exit_segm_regular_tseg2 : std_logic;
-- SJW more than 0
signal sjw_mt_zero : std_logic;
begin
---------------------------------------------------------------------------
......@@ -316,6 +323,7 @@ begin
---------------------------------------------------------------------------
sel_tseg1 <= '1' when (h_sync_valid = '1' or start_edge = '1') else
'1' when (segm_end = '1' and is_tseg2 = '1') else
'1' when (segm_end = '0' and is_tseg1 = '1') else
'0';
basic_segm_length <=
......@@ -379,11 +387,14 @@ begin
else
'0';
sjw_mt_zero <= '1' when (unsigned(sjw) > 0) else
'0';
---------------------------------------------------------------------------
-- Immediate exit occurs during PH2 when resync edge occurs.
---------------------------------------------------------------------------
exit_ph2_immediate <= '1' when (phase_err_mt_sjw = '0' and is_tseg2 = '1' and
resync_edge_valid = '1')
resync_edge_valid = '1')
else
'0';
......@@ -396,6 +407,28 @@ begin
else
'0';
---------------------------------------------------------------------------
-- TSEG1 is finished when Bit time counter reached value, but not when
-- resync-edge is there at the same time! If we did not consider resync
-- edge, we would ignore resync edge which arrives just at the same clock
-- cycle as bit time!
---------------------------------------------------------------------------
exit_segm_regular_tseg1 <= '0' when (is_tseg1 = '1' and
resync_edge_valid = '1' and
sjw_mt_zero = '1')
else
'1' when (is_tseg1 = '1' and exit_segm_regular = '1')
else
'0';
---------------------------------------------------------------------------
-- TSEG2 is finished when Bit time counter reached expected value!
---------------------------------------------------------------------------
exit_segm_regular_tseg2 <= '1' when (is_tseg2 = '1' and exit_segm_regular = '1')
else
'0';
---------------------------------------------------------------------------
-- Capture request to end of segment. Re-synchronisation is not Time Quanta
-- aligned, so we must capture the flag.
......@@ -405,8 +438,8 @@ begin
-- 3. PROP or PH1 regular segment exit.
---------------------------------------------------------------------------
exit_segm_req <= '1' when (exit_ph2_immediate = '1') else
'1' when (is_tseg2 = '1' and exit_segm_regular = '1') else
'1' when (is_tseg1 = '1' and exit_segm_regular = '1') else
'1' when (exit_segm_regular_tseg1 = '1' or
exit_segm_regular_tseg2 = '1') else
'0';
end architecture rtl;
\ No newline at end of file
......@@ -43,10 +43,14 @@
-- Purpose:
-- End of segment detector. Detects end of current segment (TSEG1 or TSEG2)
-- as a result of Hard-synchronisation, or request from Re-synchronisation.
-- Provides signal for clearing Bit Time counters.
--
--------------------------------------------------------------------------------
-- Revision History:
-- 15.02.2019 Created file
-- 08.03.2019 Separated Segment end and Bit time counter clear. This-way
-- we can distuinguish between first and second hard-sync
-- edge in TSEG1.
--------------------------------------------------------------------------------
Library ieee;
......@@ -104,10 +108,11 @@ entity segment_end_detector is
signal tq_edge_dbt : in std_logic;
-----------------------------------------------------------------------
-- Outputs - Decision that current segment should end
-- Outputs - Decision that current segment should end!
-----------------------------------------------------------------------
signal segm_end : out std_logic;
signal h_sync_valid : out std_logic
signal h_sync_valid : out std_logic;
signal bt_ctr_clear : out std_logic
);
end entity;
......@@ -117,13 +122,14 @@ architecture rtl of segment_end_detector is
-- Registers to capture requests for Hard-sync (0),
-- NBT end of segment (1), DBT end of segment (2)
---------------------------------------------------------------------------
signal req_input : std_logic_vector(2 downto 0);
signal segm_end_req_capt_d : std_logic_vector(2 downto 0);
signal segm_end_req_capt_q : std_logic_vector(2 downto 0);
signal segm_end_req_capt_ce : std_logic_vector(2 downto 0);
signal req_input : std_logic_vector(2 downto 0);
signal segm_end_req_capt_d : std_logic_vector(2 downto 0);
signal segm_end_req_capt_q : std_logic_vector(2 downto 0);
signal segm_end_req_capt_ce : std_logic_vector(2 downto 0);
signal segm_end_req_capt_clr : std_logic_vector(2 downto 0);
-- ORed flags and combinational requests
signal segm_end_req_capt_dq : std_logic_vector(2 downto 0);
signal segm_end_req_capt_dq : std_logic_vector(2 downto 0);
-- Valid requests to end segment for each Sample type (Nominal, Data)
signal segm_end_nbt_valid : std_logic;
......@@ -131,19 +137,22 @@ architecture rtl of segment_end_detector is
signal segm_end_nbt_dbt_valid : std_logic;
-- Internally generated sample point
signal sample_point : std_logic;
signal sample_point : std_logic;
-- Combinational requests to finish segment.
signal tseg1_end_req_valid : std_logic;
signal tseg2_end_req_valid : std_logic;
signal hsync_end_req_valid : std_logic;
signal tseg1_end_req_valid : std_logic;
signal tseg2_end_req_valid : std_logic;
signal hsync_end_req_valid : std_logic;
-- End of segment, internal value
signal segment_end_i : std_logic;
signal segment_end_i : std_logic;
-- Nominal / Data Time quanta are active
signal nbt_tq_active : std_logic;
signal dbt_tq_active : std_logic;
signal nbt_tq_active : std_logic;
signal dbt_tq_active : std_logic;
-- Bit time clear - internal value
signal bt_ctr_clear_i : std_logic;
begin
......@@ -157,15 +166,25 @@ begin
req_input(1) <= exit_segm_req_nbt;
req_input(2) <= exit_segm_req_dbt;
----------------------------------------------------------------------------
-- Clearing requests:
-- 1. Upon any bit time clear (which is either Segment end or Hard-sync).
-- 2. Segment end.
-- 3. Segment end.
----------------------------------------------------------------------------
segm_end_req_capt_clr(0) <= bt_ctr_clear_i;
segm_end_req_capt_clr(1) <= segment_end_i;
segm_end_req_capt_clr(2) <= segment_end_i;
segm_end_req_capture : for i in 0 to 2 generate
begin
-- Clear the flag upon real end of segment!
segm_end_req_capt_d(i) <= '0' when (segment_end_i = '1') else
segm_end_req_capt_d(i) <= '0' when (segm_end_req_capt_clr(i) = '1') else
req_input(i);
segm_end_req_capt_ce(i) <=
'1' when (segment_end_i = '1' or req_input(i) = '1') else
'1' when (segm_end_req_capt_clr(i) = '1' or req_input(i) = '1') else
'0';
end_of_segm_req_proc : process(clk_sys, res_n)
......@@ -179,12 +198,35 @@ begin
end if;
end process;
-- Request is valid either when flag is captured or when combinational
-- request is valid!
segm_end_req_capt_dq(i) <= req_input(i) OR segm_end_req_capt_q(i);
end generate;
---------------------------------------------------------------------------
-- Hard synchronisation induced end of segment request is valid when
-- both: combinational and captured requests are valid. This accounts
-- for h-sync edge in the same clock cycle as well as captured from
-- previous clock cycles in last time quanta!
---------------------------------------------------------------------------
segm_end_req_capt_dq(0) <= req_input(0) OR segm_end_req_capt_q(0);
---------------------------------------------------------------------------
-- Segment end request from NBT and DBT resynchronisation is valid
-- for each Bit segment differently.
-- For TSEG1:
-- 1. Combinational is valid! Here the request hangs (it is always due
-- to comparison with Bit time counter, so it does not have to be
-- captured)!
-- For TSEG2:
-- 2. Combinational is valid, or captured request is valid. This accounts
-- for edge in the same clock cycle, as well as immediate exit occured
-- in previous clock cycle during previous Time quanta which was
-- captured and is not present anymore!
---------------------------------------------------------------------------
segm_end_req_capt_dq(1) <= req_input(1) when (is_tseg1 = '1') else
req_input(1) OR segm_end_req_capt_q(1);
segm_end_req_capt_dq(2) <= req_input(2) when (is_tseg1 = '1') else
req_input(2) OR segm_end_req_capt_q(2);
---------------------------------------------------------------------------
-- Nominal and Data Time Quanta are active only when corresponding Sample
-- type is set!
......@@ -230,9 +272,13 @@ begin
else
'0';
---------------------------------------------------------------------------
-- Align Hard synchronisation request with Time Quanta. Note that Hard sync.
-- is only allowed in Nominal Bit-rat, thus use only Nominal Time Quanta edge!
---------------------------------------------------------------------------
hsync_end_req_valid <=
'1' when ((segm_end_req_capt_dq(0) = '1') and
(nbt_tq_active = '1' or dbt_tq_active = '1'))
(nbt_tq_active = '1'))
else
'0';
......@@ -243,14 +289,27 @@ begin
-- 2. Data Bit Time Resynchronisation signals end of segment, Data
-- Time Quanta edge and Sample control is either DATA_SAMPLE or
-- SECONDARY_SAMPLE!
-- 3. Hard synchronisation induced end of segment.
-- 3. Hard synchronisation induced end of segment in TSEG2! In TSEG1
-- segment is not ended, only Bit Time counter is restarted!
---------------------------------------------------------------------------
segment_end_i <= '1' when (tseg1_end_req_valid = '1' or
segment_end_i <= '1' when ((tseg1_end_req_valid = '1' and hsync_end_req_valid = '0') or
tseg2_end_req_valid = '1' or
hsync_end_req_valid = '1')
(hsync_end_req_valid = '1' and is_tseg2 = '1'))
else
'0';
---------------------------------------------------------------------------
-- Bit time counter clear:
-- 1. Segment end.
-- 2. Hard sync is valid. This covers the case when Hard-sync edge
-- occurs in TSEG1 and TSEG1 does not end, it just gets re-started
-- (bit time counter will be cleared)!
---------------------------------------------------------------------------
bt_ctr_clear_i <= '1' when (segment_end_i = '1' or hsync_end_req_valid = '1')
else
'0';
bt_ctr_clear <= bt_ctr_clear_i;
segm_end <= segment_end_i;
h_sync_valid <= hsync_end_req_valid;
......
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