Commit 74cace23 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Added TIMESTAMP_LOW, TIMESTAMP_HIGH registers. Needed less than 30 minutes

to do all the work. Voila, miracle of register map generator.
parent 4df62a79
......@@ -533,7 +533,7 @@ Ille Ondrej, Martin Jeřábek
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="7" columns="4">
<lyxtabular version="3" rows="8" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="1.5cm">
<column alignment="center" valignment="top" width="2cm">
......@@ -773,7 +773,7 @@ Added Register map block diagram after re-implementation of registers via
</cell>
</row>
<row>
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
 
\begin_layout Plain Layout
......@@ -782,7 +782,7 @@ Added Register map block diagram after re-implementation of registers via
 
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
 
\begin_layout Plain Layout
......@@ -791,7 +791,7 @@ Ondrej Ille
 
\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
 
\begin_layout Plain Layout
......@@ -800,7 +800,7 @@ Ondrej Ille
 
\end_inset
</cell>
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
 
\begin_layout Plain Layout
......@@ -808,6 +808,44 @@ Added CRC Wrapper.
Extended CRC description.
\end_layout
 
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
2.1.3
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Ondrej Ille
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
01-2019
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Added TIMESTAMP_LOW, TIMESTAMP_HIGH registers.
\end_layout
\end_inset
</cell>
</row>
......
This diff is collapsed.
......@@ -84,6 +84,8 @@ enum ctu_can_fd_can_registers {
CTU_CAN_FD_TX_COUNTER = 0x80,
CTU_CAN_FD_DEBUG_REGISTER = 0x84,
CTU_CAN_FD_YOLO_REG = 0x88,
CTU_CAN_FD_TIMESTAMP_LOW = 0x8c,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x90,
CTU_CAN_FD_TXTB1_DATA_1 = 0x100,
CTU_CAN_FD_TXTB1_DATA_2 = 0x104,
CTU_CAN_FD_TXTB1_DATA_20 = 0x14c,
......@@ -909,6 +911,22 @@ union ctu_can_fd_yolo_reg {
} s;
};
union ctu_can_fd_timestamp_low {
uint32_t u32;
struct ctu_can_fd_timestamp_low_s {
/* TIMESTAMP_LOW */
uint32_t timestamp_low : 32;
} s;
};
union ctu_can_fd_timestamp_high {
uint32_t u32;
struct ctu_can_fd_timestamp_high_s {
/* TIMESTAMP_HIGH */
uint32_t timestamp_high : 32;
} s;
};
union ctu_can_fd_log_trig_config {
uint32_t u32;
struct ctu_can_fd_log_trig_config_s {
......
......@@ -1401,6 +1401,52 @@
<ipxact:modifiedWriteValue>clear</ipxact:modifiedWriteValue>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>TIMESTAMP_HIGH</ipxact:name>
<ipxact:displayName>TIMESTAMP_HIGH</ipxact:displayName>
<ipxact:description>Register with mirrored values of timestamp input. Bits 63:32 of timestamp input are available from this register. No synchronisation, nor shadowing is implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of proper read from both registers, since overflow of TIMESTAMP_LOW might occur between read of TIMESTAMP_LOW and TIMESTAMP_HIGH.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h90</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-only</ipxact:access>
<ipxact:field>
<ipxact:name>TIMESTAMP_HIGH</ipxact:name>
<ipxact:displayName>TIMESTAMP_HIGH</ipxact:displayName>
<ipxact:description>Bits 63:32 of timestamp input.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>00</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>32</ipxact:bitWidth>
<ipxact:access>read-only</ipxact:access>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>TIMESTAMP_LOW</ipxact:name>
<ipxact:displayName>TIMESTAMP_LOW</ipxact:displayName>
<ipxact:description>Register with mirrored values of timestamp input. Bits 31:0 of timestamp input are available from this register. No synchronisation, nor shadowing is implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of proper read from both registers, since overflow of TIMESTAMP_LOW might occur between read of TIMESTAMP_LOW and TIMESTAMP_HIGH.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h8C</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-only</ipxact:access>
<ipxact:field>
<ipxact:name>TIMESTAMP_LOW</ipxact:name>
<ipxact:displayName>TIMESTAMP_LOW</ipxact:displayName>
<ipxact:description>Bits 31:0 of timestamp input.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>32</ipxact:bitWidth>
<ipxact:access>read-only</ipxact:access>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>YOLO_REG</ipxact:name>
<ipxact:displayName>YOLO_REG</ipxact:displayName>
......
......@@ -399,7 +399,7 @@ architecture rtl of CAN_top_level is
signal br_shifted : std_logic;
--Event logging finsihed
signal loger_finished : std_logic;
signal loger_finished : std_logic;
----------------------------------------------------------------------------
......@@ -536,6 +536,7 @@ begin
srd => srd,
swr => swr,
sbe => sbe,
timestamp => timestamp,
drv_bus => drv_bus,
stat_bus => stat_bus,
rx_read_buff => rx_read_buff,
......
......@@ -140,6 +140,7 @@ package can_components is
signal srd : in std_logic;
signal swr : in std_logic;
signal sbe : in std_logic_vector(3 downto 0);
signal timestamp : in std_logic_vector(63 downto 0);
signal drv_bus : out std_logic_vector(1023 downto 0);
signal stat_bus : in std_logic_vector(511 downto 0);
signal rx_read_buff : in std_logic_vector(31 downto 0);
......
......@@ -102,6 +102,8 @@ package can_fd_register_map is
constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"080";
constant DEBUG_REGISTER_ADR : std_logic_vector(11 downto 0) := x"084";
constant YOLO_REG_ADR : std_logic_vector(11 downto 0) := x"088";
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"08C";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"090";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......@@ -1026,6 +1028,37 @@ package can_fd_register_map is
-- YOLO_REG register reset values
constant YOLO_VAL_RSTVAL : std_logic_vector(31 downto 0) := x"DEADBEEF";
------------------------------------------------------------------------------
-- TIMESTAMP_LOW register
--
-- Register with mirrored values of timestamp input. Bits 31:0 of timestamp in
-- put are available from this register. No synchronisation, nor shadowing is
-- implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of pr
-- oper read from both registers, since overflow of TIMESTAMP_LOW might occur
-- between read of TIMESTAMP_LOW and TIMESTAMP_HIGH.
------------------------------------------------------------------------------
constant TIMESTAMP_LOW_L : natural := 0;
constant TIMESTAMP_LOW_H : natural := 31;
-- TIMESTAMP_LOW register reset values
constant TIMESTAMP_LOW_RSTVAL : std_logic_vector(31 downto 0) := x"00000000";
------------------------------------------------------------------------------
-- TIMESTAMP_HIGH register
--
-- Register with mirrored values of timestamp input. Bits 63:32 of timestamp i
-- nput are available from this register. No synchronisation, nor shadowing is
-- implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of p
-- roper read from both registers, since overflow of TIMESTAMP_LOW might occur
-- between read of TIMESTAMP_LOW and TIMESTAMP_HIGH.
------------------------------------------------------------------------------
constant TIMESTAMP_HIGH_L : natural := 0;
constant TIMESTAMP_HIGH_H : natural := 31;
-- TIMESTAMP_HIGH register reset values
constant TIMESTAMP_HIGH_RSTVAL
: std_logic_vector(31 downto 0) := x"00000000";
------------------------------------------------------------------------------
-- TXTB1_DATA_1 register
--
......
......@@ -104,6 +104,8 @@ package can_registers_pkg is
tx_counter : std_logic_vector(31 downto 0);
debug_register : std_logic_vector(31 downto 0);
yolo_reg : std_logic_vector(31 downto 0);
timestamp_low : std_logic_vector(31 downto 0);
timestamp_high : std_logic_vector(31 downto 0);
end record;
......
......@@ -80,10 +80,10 @@ end entity control_registers_reg_map;
architecture rtl of control_registers_reg_map is
signal reg_sel : std_logic_vector(34 downto 0);
signal reg_sel : std_logic_vector(36 downto 0);
constant ADDR_VECT
: std_logic_vector(209 downto 0) := "100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(1119 downto 0);
: std_logic_vector(221 downto 0) := "100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(1183 downto 0);
signal read_data_mask_n : std_logic_vector(31 downto 0);
signal control_registers_out_i : Control_registers_out_t;
signal read_mux_ena : std_logic;
......@@ -96,7 +96,7 @@ begin
address_decoder_control_registers_comp : address_decoder
generic map(
address_width => 6 ,
address_entries => 35 ,
address_entries => 37 ,
addr_vect => ADDR_VECT ,
registered_out => false ,
reset_polarity => RESET_POLARITY
......@@ -757,7 +757,7 @@ begin
data_mux_control_registers_comp : data_mux
generic map(
data_out_width => 32 ,
data_in_width => 1120 ,
data_in_width => 1184 ,
sel_width => 6 ,
registered_out => REGISTERED_READ ,
reset_polarity => RESET_POLARITY
......@@ -776,6 +776,12 @@ begin
-- Read data driver
------------------------------------------------------------------------------
read_data_mux_in <=
-- Adress:144
control_registers_in.timestamp_high &
-- Adress:140
control_registers_in.timestamp_low &
-- Adress:136
control_registers_in.yolo_reg &
......
......@@ -195,6 +195,9 @@ entity memory_registers is
signal swr :in std_logic;
signal sbe :in std_logic_vector(3 downto 0);
-- Timestamp input
signal timestamp :in std_logic_vector(63 downto 0);
-- Driving and Status Bus
signal drv_bus :out std_logic_vector(1023 downto 0)
:= (OTHERS => '0');
......@@ -1417,6 +1420,28 @@ begin
end block yolo_register_block;
---------------------------------------------------------------------------
-- TIMESTAMP_LOW, TIMESTAMP_HIGH registers
---------------------------------------------------------------------------
timestamp_registers_block : block
constant ts_low_l : natural := Control_registers_in.timestamp_low'length;
constant ts_high_l : natural := Control_registers_in.timestamp_high'length;
begin
Control_registers_in.timestamp_low(
align_reg_to_wrd(TIMESTAMP_LOW_H, ts_low_l) downto
align_reg_to_wrd(TIMESTAMP_LOW_L, ts_low_l)) <=
timestamp(31 downto 0);
Control_registers_in.timestamp_high(
align_reg_to_wrd(TIMESTAMP_HIGH_H, ts_high_l) downto
align_reg_to_wrd(TIMESTAMP_HIGH_L, ts_high_l)) <=
timestamp(63 downto 32);
end block timestamp_registers_block;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Event Logger - Write registers to Driving Bus Connection
......
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