Commit 741016af authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

1. Added RX Buffer not empty interrupt

2. Added TXT Buffer HW command interrupt
3. Removed wake_up valid, since it was unused.
parent 04a81323
......@@ -4903,11 +4903,11 @@ Reserved\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
TXBHCI\end_layout
 
\end_inset
</cell>
......@@ -4915,7 +4915,7 @@ Reserved\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
BSI\end_layout
RBNEI\end_layout
 
\end_inset
</cell>
......@@ -4923,7 +4923,7 @@ BSI\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
RFI\end_layout
BSI\end_layout
 
\end_inset
</cell>
......@@ -4931,7 +4931,7 @@ RFI\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
LFI\end_layout
RFI\end_layout
 
\end_inset
</cell>
......@@ -4981,7 +4981,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......@@ -5118,7 +5118,7 @@ Field name\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
BEI\end_layout
LFI\end_layout
 
\end_inset
</cell>
......@@ -5126,7 +5126,7 @@ BEI\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
ALI\end_layout
BEI\end_layout
 
\end_inset
</cell>
......@@ -5134,7 +5134,7 @@ ALI\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
EPI\end_layout
ALI\end_layout
 
\end_inset
</cell>
......@@ -5142,7 +5142,7 @@ EPI\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
EPI\end_layout
 
\end_inset
</cell>
......@@ -5216,7 +5216,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......@@ -5289,6 +5289,12 @@ RFI Receive buffer full interrupt
\begin_layout Description
BSI Bit-rate shifted interrupt
\end_layout
\begin_layout Description
RBNEI Receive buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt.
\end_layout
\begin_layout Description
TXBHCI TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core, this interrupt will be acivated.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
\end_inset
......@@ -5445,19 +5451,19 @@ Reserved\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
INT_ENA_SET[11:8]\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
INT_ENA_SET[10:8]\end_layout
INT_ENA_SET[11:8]\end_layout
 
\end_inset
</cell>
......@@ -5465,7 +5471,7 @@ INT_ENA_SET[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_ENA_SET[10:8]\end_layout
INT_ENA_SET[11:8]\end_layout
 
\end_inset
</cell>
......@@ -5473,7 +5479,7 @@ INT_ENA_SET[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_ENA_SET[10:8]\end_layout
INT_ENA_SET[11:8]\end_layout
 
\end_inset
</cell>
......@@ -5523,7 +5529,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......@@ -5960,19 +5966,19 @@ Reserved\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
INT_ENA_CLR[11:8]\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
INT_ENA_CLR[10:8]\end_layout
INT_ENA_CLR[11:8]\end_layout
 
\end_inset
</cell>
......@@ -5980,7 +5986,7 @@ INT_ENA_CLR[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_ENA_CLR[10:8]\end_layout
INT_ENA_CLR[11:8]\end_layout
 
\end_inset
</cell>
......@@ -5988,7 +5994,7 @@ INT_ENA_CLR[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_ENA_CLR[10:8]\end_layout
INT_ENA_CLR[11:8]\end_layout
 
\end_inset
</cell>
......@@ -6038,7 +6044,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......@@ -6475,19 +6481,19 @@ Reserved\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
INT_MASK_SET[11:8]\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
INT_MASK_SET[10:8]\end_layout
INT_MASK_SET[11:8]\end_layout
 
\end_inset
</cell>
......@@ -6495,7 +6501,7 @@ INT_MASK_SET[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_MASK_SET[10:8]\end_layout
INT_MASK_SET[11:8]\end_layout
 
\end_inset
</cell>
......@@ -6503,7 +6509,7 @@ INT_MASK_SET[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_MASK_SET[10:8]\end_layout
INT_MASK_SET[11:8]\end_layout
 
\end_inset
</cell>
......@@ -6553,7 +6559,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......@@ -6990,19 +6996,19 @@ Reserved\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
INT_MASK_CLR[11:8]\end_layout
 
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
INT_MASK_CLR[10:8]\end_layout
INT_MASK_CLR[11:8]\end_layout
 
\end_inset
</cell>
......@@ -7010,7 +7016,7 @@ INT_MASK_CLR[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_MASK_CLR[10:8]\end_layout
INT_MASK_CLR[11:8]\end_layout
 
\end_inset
</cell>
......@@ -7018,7 +7024,7 @@ INT_MASK_CLR[10:8]\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
INT_MASK_CLR[10:8]\end_layout
INT_MASK_CLR[11:8]\end_layout
 
\end_inset
</cell>
......@@ -7068,7 +7074,7 @@ Reset value\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
-\end_layout
0\end_layout
 
\end_inset
</cell>
......
......@@ -203,23 +203,25 @@ union int_stat {
uint32_t ti : 1;
uint32_t ei : 1;
uint32_t doi : 1;
uint32_t reserved_4 : 1;
uint32_t epi : 1;
uint32_t ali : 1;
uint32_t bei : 1;
uint32_t lfi : 1;
uint32_t rfi : 1;
uint32_t bsi : 1;
uint32_t reserved_31_11 : 21;
uint32_t rbnei : 1;
uint32_t txbhci : 1;
uint32_t reserved_31_12 : 20;
#else
uint32_t reserved_31_11 : 21;
uint32_t reserved_31_12 : 20;
uint32_t txbhci : 1;
uint32_t rbnei : 1;
uint32_t bsi : 1;
uint32_t rfi : 1;
uint32_t lfi : 1;
uint32_t bei : 1;
uint32_t ali : 1;
uint32_t epi : 1;
uint32_t reserved_4 : 1;
uint32_t doi : 1;
uint32_t ei : 1;
uint32_t ti : 1;
......@@ -233,11 +235,11 @@ union int_ena_set {
struct int_ena_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* INT_ENA_SET */
uint32_t int_ena_set : 11;
uint32_t reserved_31_11 : 21;
uint32_t int_ena_set : 12;
uint32_t reserved_31_12 : 20;
#else
uint32_t reserved_31_11 : 21;
uint32_t int_ena_set : 11;
uint32_t reserved_31_12 : 20;
uint32_t int_ena_set : 12;
#endif
} s;
};
......@@ -247,11 +249,11 @@ union int_ena_clr {
struct int_ena_clr_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* INT_ENA_CLR */
uint32_t int_ena_clr : 11;
uint32_t reserved_31_11 : 21;
uint32_t int_ena_clr : 12;
uint32_t reserved_31_12 : 20;
#else
uint32_t reserved_31_11 : 21;
uint32_t int_ena_clr : 11;
uint32_t reserved_31_12 : 20;
uint32_t int_ena_clr : 12;
#endif
} s;
};
......@@ -261,11 +263,11 @@ union int_mask_set {
struct int_mask_set_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* INT_MASK_SET */
uint32_t int_mask_set : 11;
uint32_t reserved_31_11 : 21;
uint32_t int_mask_set : 12;
uint32_t reserved_31_12 : 20;
#else
uint32_t reserved_31_11 : 21;
uint32_t int_mask_set : 11;
uint32_t reserved_31_12 : 20;
uint32_t int_mask_set : 12;
#endif
} s;
};
......@@ -275,11 +277,11 @@ union int_mask_clr {
struct int_mask_clr_s {
#ifdef __BIG_ENDIAN_BITFIELD
/* INT_MASK_CLR */
uint32_t int_mask_clr : 11;
uint32_t reserved_31_11 : 21;
uint32_t int_mask_clr : 12;
uint32_t reserved_31_12 : 20;
#else
uint32_t reserved_31_11 : 21;
uint32_t int_mask_clr : 11;
uint32_t reserved_31_12 : 20;
uint32_t int_mask_clr : 12;
#endif
} s;
};
......
......@@ -584,7 +584,7 @@
<ipxact:name>EPI</ipxact:name>
<ipxact:displayName>EPI</ipxact:displayName>
<ipxact:description>Node became error passive or bus off interrupt</ipxact:description>
<ipxact:bitOffset>5</ipxact:bitOffset>
<ipxact:bitOffset>4</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
......@@ -596,7 +596,7 @@
<ipxact:name>ALI</ipxact:name>
<ipxact:displayName>ALI</ipxact:displayName>
<ipxact:description>Arbitration lost interrupt</ipxact:description>
<ipxact:bitOffset>6</ipxact:bitOffset>
<ipxact:bitOffset>5</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
......@@ -608,7 +608,7 @@
<ipxact:name>BEI</ipxact:name>
<ipxact:displayName>BEI</ipxact:displayName>
<ipxact:description>Bus Error interrupt</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:bitOffset>6</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
......@@ -620,7 +620,7 @@
<ipxact:name>LFI</ipxact:name>
<ipxact:displayName>LFI</ipxact:displayName>
<ipxact:description>Event logging finished interrupt</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
......@@ -632,7 +632,7 @@
<ipxact:name>RFI</ipxact:name>
<ipxact:displayName>RFI</ipxact:displayName>
<ipxact:description>Receive buffer full interrupt</ipxact:description>
<ipxact:bitOffset>9</ipxact:bitOffset>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
......@@ -644,6 +644,18 @@
<ipxact:name>BSI</ipxact:name>
<ipxact:displayName>BSI</ipxact:displayName>
<ipxact:description>Bit-rate shifted interrupt</ipxact:description>
<ipxact:bitOffset>9</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>RBNEI</ipxact:name>
<ipxact:displayName>RBNEI</ipxact:displayName>
<ipxact:description>Receive buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt.</ipxact:description>
<ipxact:bitOffset>10</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -652,6 +664,18 @@
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>TXBHCI</ipxact:name>
<ipxact:displayName>TXBHCI</ipxact:displayName>
<ipxact:description>TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core, this interrupt will be acivated.</ipxact:description>
<ipxact:bitOffset>11</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>RX_SETTINGS</ipxact:name>
......@@ -707,7 +731,7 @@
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>11</ipxact:bitWidth>
<ipxact:bitWidth>12</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
......@@ -729,7 +753,7 @@
<ipxact:value>'h0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>11</ipxact:bitWidth>
<ipxact:bitWidth>12</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
......@@ -751,7 +775,7 @@
<ipxact:value>'h0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>11</ipxact:bitWidth>
<ipxact:bitWidth>12</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
......@@ -773,7 +797,7 @@
<ipxact:value>'h0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>11</ipxact:bitWidth>
<ipxact:bitWidth>12</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
......
......@@ -159,7 +159,6 @@ entity core_top is
--Interrupt Manager Interface--
-------------------------------
signal arbitration_lost_out :out std_logic; --Arbitration was lost input
signal wake_up_valid :out std_logic; --Wake up appeared
--Message stored in CAN Core was sucessfully transmitted
signal tx_finished :out std_logic;
......@@ -845,7 +844,6 @@ begin
--Output propagation
arbitration_lost_out <= arbitration_lost;
wake_up_valid <= '0'; --No slepp mode implemented
tx_finished <= tran_valid;
sof_pulse <= sof_pulse_r;
......
......@@ -645,12 +645,13 @@ begin
error_passive_changed => error_passive_changed,
error_warning_limit => error_warning_limit,
arbitration_lost => arbitration_lost,
wake_up_valid => wake_up_valid,
tx_finished => tx_finished,
br_shifted => br_shifted,
rx_message_disc => rx_message_disc,
rec_message_valid => rec_message_valid,
rx_full => rx_full,
rx_empty => rx_empty,
txt_hw_cmd => txt_hw_cmd,
loger_finished => loger_finished,
drv_bus => drv_bus,
int_out => int,
......@@ -688,7 +689,6 @@ begin
rec_dram_word_out => rec_dram_word,
rec_dram_addr_out => rec_dram_addr,
arbitration_lost_out => arbitration_lost,
wake_up_valid => wake_up_valid,
tx_finished => tx_finished,
br_shifted => br_shifted,
error_valid => error_valid,
......
......@@ -56,12 +56,14 @@
-- interrupt enable and interrupt mask. Interrupts changed to
-- be level based instead of edge based with fixed duration. This
-- is more fitting for SocketCAN implementation.
-- 12.3.2018 Implemented RX Buffer not empty and TX Buffer HW command INT.
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE WORK.CANconstants.ALL;
use work.CAN_FD_register_map.all;
entity intManager is
GENERIC(
......@@ -90,9 +92,6 @@ entity intManager is
--Arbitration was lost input
signal arbitration_lost :in std_logic;
--Wake up appeared
signal wake_up_valid :in std_logic;
--Message stored in CAN Core was sucessfully transmitted
signal tx_finished :in std_logic;
......@@ -109,6 +108,12 @@ entity intManager is
--RX Buffer is full (the last income message filled the remaining space)
--NOTE! rec_message_valid will be in logic one for two clock cycles
--Recieve buffer is empty
signal rx_empty :in std_logic;
--HW commands on TXT Buffer
signal txt_hw_cmd :in txt_hw_cmd_type;
--Event logger
signal loger_finished :in std_logic; --Event logging finsihed
......@@ -167,18 +172,21 @@ begin
'0';
-- Interrupt register masking and enabling
int_input_active(BUS_ERR_INT) <= error_valid;
int_input_active(ARB_LST_INT) <= arbitration_lost;
int_input_active(ERR_PAS_INT) <= error_passive_changed;
int_input_active(WAKE_INT) <= wake_up_valid;
int_input_active(DOV_INT) <= rx_message_disc;
int_input_active(ERR_WAR_INT) <= error_warning_limit;
int_input_active(TX_INT) <= tx_finished;
int_input_active(RX_INT) <= rec_message_valid;
int_input_active(LOG_FIN_INT) <= loger_finished;
int_input_active(RX_FULL_INT) <= rx_full;
int_input_active(BRS_INT) <= br_shifted;
int_input_active(BEI_IND) <= error_valid;
int_input_active(ALI_IND) <= arbitration_lost;
int_input_active(EPI_IND) <= error_passive_changed;
int_input_active(DOI_IND) <= rx_message_disc;
int_input_active(EI_IND) <= error_warning_limit;
int_input_active(TI_IND) <= tx_finished;
int_input_active(RI_IND) <= rec_message_valid;
int_input_active(LFI_IND) <= loger_finished;
int_input_active(RFI_IND) <= rx_full;
int_input_active(BSI_IND) <= br_shifted;
int_input_active(RBNEI_IND) <= not rx_empty;
int_input_active(TXBHCI_IND) <= '1' when (txt_hw_cmd.lock = '1' or
txt_hw_cmd.unlock = '1')
else
'0';
int_proc:process(res_n, clk_sys)
begin
......
......@@ -323,12 +323,14 @@ package CAN_FD_register_map is
constant TI_IND : natural := 1;
constant EI_IND : natural := 2;
constant DOI_IND : natural := 3;
constant EPI_IND : natural := 5;
constant ALI_IND : natural := 6;
constant BEI_IND : natural := 7;
constant LFI_IND : natural := 8;
constant RFI_IND : natural := 9;
constant BSI_IND : natural := 10;
constant EPI_IND : natural := 4;
constant ALI_IND : natural := 5;
constant BEI_IND : natural := 6;
constant LFI_IND : natural := 7;
constant RFI_IND : natural := 8;
constant BSI_IND : natural := 9;
constant RBNEI_IND : natural := 10;
constant TXBHCI_IND : natural := 11;
-- INT_STAT register reset values