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CTU CAN FD IP Core
Commit 73a51f21 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Modified benches and Core top to support Unknown OP State 

and removed obsolete unknown state error.
parent aa35db00
Pipeline #1560 passed with stages
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      Showing with 43 additions and 43 deletions
      src/CAN_Core/core_top.vhd
      View file @ 73a51f21
      ......@@ -391,6 +391,8 @@ entity core_top is
      signal is_idle : std_logic;
      signal alc : std_logic_vector(7 downto 0);
      signal unknown_OP_state : std_logic;
      -- Transcieve buffer output
      signal tran_dlc : std_logic_vector(3 downto 0);
      signal tran_is_rtr : std_logic;
      ......@@ -590,6 +592,7 @@ begin
      tran_data_valid_in => tran_frame_valid_in,
      set_transciever => set_transciever,
      set_reciever => set_reciever,
      unknown_OP_state => unknown_OP_state,
      is_idle => is_idle,
      tran_trig => tran_trig,
      rec_trig => rec_trig,
      ......@@ -651,7 +654,6 @@ begin
      form_Error => form_Error,
      CRC_Error => CRC_Error,
      ack_Error => ack_Error,
      unknown_state_Error => unknown_state_Error,
      bit_Error_valid => bit_Error_valid,
      stuff_Error_valid => stuff_Error_valid,
      ......@@ -678,6 +680,8 @@ begin
      destuff_length => bds_length,
      dst_ctr => st_ctr_resolved,
      unknown_OP_state => unknown_OP_state,
      crc_enable => crc_enable,
      crc15 => crc15,
      crc17 => crc17,
      ......@@ -728,7 +732,6 @@ begin
      form_Error => form_Error,
      CRC_Error => CRC_Error,
      ack_Error => ack_Error,
      unknown_state_Error => unknown_state_Error,
      bit_Error_valid => bit_Error_valid,
      stuff_Error_valid => stuff_Error_valid,
      ......@@ -957,9 +960,9 @@ begin
      ----------------------------------------------------------------------------
      -- Multiplexing of stuff counter and destuff counter
      ----------------------------------------------------------------------------
      st_ctr_resolved <= dst_ctr when OP_State = reciever else
      bst_ctr when OP_State = transciever else
      0;
      st_ctr_resolved <= dst_ctr when (OP_State = reciever) else
      bst_ctr when (OP_State = transciever) else
      0;
      ----------------------------------------------------------------------------
      ......@@ -1010,14 +1013,14 @@ begin
      -- detection during Data Phase!!!
      ----------------------------------------------------------------------------
      bs_trig <= sync_nbt_del_1 when sp_control_int = NOMINAL_SAMPLE else
      sync_dbt_del_1 when sp_control_int = DATA_SAMPLE else
      sync_dbt_del_1 when sp_control_int = SECONDARY_SAMPLE else
      bs_trig <= sync_nbt_del_1 when (sp_control_int = NOMINAL_SAMPLE) else
      sync_dbt_del_1 when (sp_control_int = DATA_SAMPLE) else
      sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
      '0';
      bds_trig <= sample_nbt_del_1 when sp_control_int = NOMINAL_SAMPLE else
      sample_dbt_del_1 when sp_control_int = DATA_SAMPLE else
      sync_dbt_del_1 when sp_control_int = SECONDARY_SAMPLE else
      bds_trig <= sample_nbt_del_1 when (sp_control_int = NOMINAL_SAMPLE) else
      sample_dbt_del_1 when (sp_control_int = DATA_SAMPLE) else
      sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
      '0';
      ----------------------------------------------------------------------------
      ......@@ -1055,9 +1058,9 @@ begin
      else rec_trig;
      crc_tx_wbs_trig <= '0' when (fixed_stuff = '1' and data_halt = '1') else
      sync_nbt_del_2 when sp_control_int = NOMINAL_SAMPLE else
      sync_dbt_del_2 when sp_control_int = DATA_SAMPLE else
      sync_dbt_del_2 when sp_control_int = SECONDARY_SAMPLE else
      sync_nbt_del_2 when (sp_control_int = NOMINAL_SAMPLE) else
      sync_dbt_del_2 when (sp_control_int = DATA_SAMPLE) else
      sync_dbt_del_2 when (sp_control_int = SECONDARY_SAMPLE) else
      '0';
      error_valid <= error_valid_int;
      ......@@ -1203,7 +1206,7 @@ begin
      stat_bus(STAT_FORM_ERROR_INDEX) <= form_Error;
      stat_bus(STAT_CRC_ERROR_INDEX) <= CRC_Error;
      stat_bus(STAT_ACK_ERROR_INDEX) <= ack_Error;
      stat_bus(STAT_UNKNOWN_STATE_ERROR_INDEX) <= unknown_state_Error;
      stat_bus(STAT_UNKNOWN_STATE_ERROR_INDEX) <= '0';
      stat_bus(STAT_BIT_STUFF_ERROR_INDEX)
      <= bit_Error_valid or stuff_Error_valid;
      ......
      src/CAN_Core/faultConf.vhd
      View file @ 73a51f21
      ......@@ -127,10 +127,6 @@ entity faultConf is
      signal CRC_Error :in std_logic; --CRC Error from PC State
      signal ack_Error :in std_logic; --Acknowledge Error from PC
      -- Some of the state machines, or signals
      -- reached unknown state!! Shouldnt happend!!
      signal unknown_state_Error :in std_logic;
      -- Error signal for PC control FSM from fault
      -- confinement unit (Bit error or Stuff Error appeared)
      signal bit_Error_valid :out std_logic;
      ......
      src/CAN_Core/operationControl.vhd
      View file @ 73a51f21
      ......@@ -77,6 +77,8 @@ entity operationControl is
      signal is_idle :in std_logic; --Unit is idle
      signal unknown_OP_state :out std_logic;
      -- Bit time triggering signals
      signal tran_trig :in std_logic;
      signal rec_trig :in std_logic;
      ......@@ -111,10 +113,13 @@ begin
      if (res_n = ACT_RESET) then
      OP_State_r <= integrating;
      integ_counter <= 1;
      unknown_OP_state <= '0';
      elsif rising_edge(clk_sys) then
      -- Presetting the registers to avoid latches
      OP_State_r <= OP_State_r;
      integ_counter <= integ_counter;
      unknown_OP_state <= '0';
      if (set_transciever = '1') then
      OP_State_r <= transciever;
      ......@@ -180,7 +185,7 @@ begin
      OP_State_r <= idle;
      end if;
      when others =>
      report "Unknown operational state" severity failure;
      unknown_OP_state <= '1';
      end case;
      end if;
      end if;
      ......
      src/CAN_Core/protocolControl.vhd
      View file @ 73a51f21
      ......@@ -315,6 +315,9 @@ entity protocolControl is
      --Arbitration lost capture
      signal alc :out std_logic_vector(7 downto 0);
      --Unknown Operational state -> Error frame!
      signal unknown_OP_state :in std_logic;
      -------------------------------
      --Fault confinement Interface--
      ......@@ -325,11 +328,7 @@ entity protocolControl is
      --Error signals for fault confinement
      signal form_Error :out std_logic; --Form Error
      signal CRC_Error :out std_logic; --CRC Error
      signal ack_Error :out std_logic; --Acknowledge error
      --Some of the state machines,
      --or signals reached unknown state!!
      signal unknown_state_Error :out std_logic;
      signal ack_Error :out std_logic; --Acknowledge error
      --Error signal for PC control FSM from fault confinement
      --unit (Bit error or Stuff Error appeared)
      ......@@ -1164,7 +1163,9 @@ begin
      if (drv_ena = '0') then
      PC_State <= off;
      elsif (bit_Error_valid = '1' or stuff_Error_valid = '1') then
      elsif (bit_Error_valid = '1' or stuff_Error_valid = '1' or
      unknown_OP_state = '1')
      then
      PC_State <= error;
      FSM_preset <= '1';
      ......
      src/Libraries/CANcomponents.vhd
      View file @ 73a51f21
      ......@@ -590,9 +590,10 @@ package CANcomponents is
      signal set_transciever : in std_logic;
      signal set_reciever : in std_logic;
      signal is_idle : in std_logic;
      signal unknown_OP_state : out std_logic;
      signal tran_trig : in std_logic;
      signal rec_trig : in std_logic;
      signal data_rx : std_logic;
      signal data_rx : in std_logic;
      signal OP_State : out oper_mode_type
      );
      end component;
      ......@@ -642,7 +643,6 @@ package CANcomponents is
      signal form_Error : out std_logic;
      signal CRC_Error : out std_logic;
      signal ack_Error : out std_logic;
      signal unknown_state_Error : out std_logic;
      signal bit_Error_valid : in std_logic;
      signal stuff_Error_valid : in std_logic;
      signal inc_one : out std_logic;
      ......@@ -663,6 +663,7 @@ package CANcomponents is
      signal destuff_length : out std_logic_vector(2 downto 0);
      signal dst_ctr : in natural range 0 to 7;
      signal crc_enable : out std_logic;
      signal unknown_OP_state : in std_logic;
      signal crc15 : in std_logic_vector(14 downto 0);
      signal crc17 : in std_logic_vector(16 downto 0);
      signal crc21 : in std_logic_vector(20 downto 0);
      ......@@ -699,7 +700,6 @@ package CANcomponents is
      signal form_Error : in std_logic;
      signal CRC_Error : in std_logic;
      signal ack_Error : in std_logic;
      signal unknown_state_Error : in std_logic;
      signal bit_Error_valid : out std_logic;
      signal stuff_Error_valid : out std_logic;
      signal inc_one : in std_logic;
      ......
      test/unit/Fault_confinement/Fault_confinement_tb.vhd
      View file @ 73a51f21
      ......@@ -107,10 +107,6 @@ architecture Fault_Confinement_unit_test of CAN_test is
      -- Acknowledge Error from PC
      signal ack_Error : std_logic := '0';
      -- Some of the state machines, or signals
      -- reached unknown state!! Shouldnt happend!!
      signal unknown_state_Error : std_logic := '0';
      -- Error signal for PC control FSM from fault
      -- confinement unit (Bit error or Stuff Error appeared)
      signal bit_Error_valid : std_logic;
      ......@@ -197,7 +193,6 @@ begin
      form_Error => form_Error,
      CRC_Error => CRC_Error,
      ack_Error => ack_Error,
      unknown_state_Error => unknown_state_Error,
      bit_Error_valid => bit_Error_valid,
      stuff_Error_valid => stuff_Error_valid,
      bit_Error_out => bit_Error_out,
      ......
      test/unit/Protocol_Control/Protocol_Control_tb.vhd
      View file @ 73a51f21
      ......@@ -113,7 +113,7 @@
      -- RX Storing protocol.
      -- 2. Added dynamically generated stuff lenght and SW model
      -- for grey coding of sutff length.
      --
      -- 13.7.2018 Added Unknown operational state signals!
      --------------------------------------------------------------------------------
      Library ieee;
      ......@@ -227,9 +227,6 @@ architecture Protocol_Control_unit_test of CAN_test is
      -- Acknowledge error
      signal ack_Error_1 : std_logic;
      -- Protocol control in unknown state
      signal unknown_state_Error_1 : std_logic;
      -- Bit error is valid
      signal bit_Error_valid_1 : std_logic;
      ......@@ -310,6 +307,9 @@ architecture Protocol_Control_unit_test of CAN_test is
      -- Internal loopBack enabled (for Bus monitoring mode)
      signal int_loop_back_ena_1 : std_logic;
      -- Unknown operational state
      signal unknown_OP_state_1 : std_logic;
      -- Protocol state output.
      signal PC_State_out_1 : protocol_type;
      ......@@ -393,9 +393,6 @@ architecture Protocol_Control_unit_test of CAN_test is
      -- Acknowledge error
      signal ack_Error_2 : std_logic;
      -- Protocol control in unknown state
      signal unknown_state_Error_2 : std_logic;
      -- Bit error is valid
      signal bit_Error_valid_2 : std_logic;
      ......@@ -477,6 +474,9 @@ architecture Protocol_Control_unit_test of CAN_test is
      -- Internal loopBack enabled (for Bus monitoring mode)
      signal int_loop_back_ena_2 : std_logic;
      -- Unknown operational state
      signal unknown_OP_state_2 : std_logic;
      -- Protocol state output.
      signal PC_State_out_2 : protocol_type;
      ......@@ -845,9 +845,9 @@ begin
      form_Error => form_Error_1,
      CRC_Error => CRC_Error_1,
      ack_Error => ack_Error_1,
      unknown_state_Error => unknown_state_Error_1,
      bit_Error_valid => bit_Error_valid_1,
      stuff_Error_valid => stuff_Error_valid_1,
      unknown_OP_state => unknown_OP_state_1,
      inc_one => inc_one_1,
      inc_eight => inc_eight_1,
      dec_one => dec_one_1,
      ......@@ -920,9 +920,9 @@ begin
      form_Error => form_Error_2,
      CRC_Error => CRC_Error_2,
      ack_Error => ack_Error_2,
      unknown_state_Error => unknown_state_Error_2,
      bit_Error_valid => bit_Error_valid_2,
      stuff_Error_valid => stuff_Error_valid_2,
      unknown_OP_state => unknown_OP_state_2,
      inc_one => inc_one_2,
      inc_eight => inc_eight_2,
      dec_one => dec_one_2,
      ......
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