Commit 6c64503d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Brought up overload feature test.

parent 8478cf37
......@@ -37,8 +37,7 @@
--------------------------------------------------------------------------------
-- Purpose:
-- Feature test for setting error counters from user and its appropriate fault
-- confinement state manipulation!
-- Feature test for generation of overload frame.
--
--------------------------------------------------------------------------------
-- Revision History:
......@@ -59,120 +58,97 @@ use work.CAN_FD_register_map.all;
package overload_feature is
procedure overload_feature_exec(
variable outcome : inout boolean;
signal rand_ctr :inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 :inout Avalon_mem_type;
signal mem_bus_2 :inout Avalon_mem_type;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal bus_level :in std_logic;
signal drv_bus_1 :in std_logic_vector(1023 downto 0);
signal drv_bus_2 :in std_logic_vector(1023 downto 0);
signal stat_bus_1 :in std_logic_vector(511 downto 0);
signal stat_bus_2 :in std_logic_vector(511 downto 0);
signal bl_inject :inout std_logic;
signal bl_force :inout boolean
);
procedure overload_feature_exec(
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0);
signal bl_inject : inout std_logic;
signal bl_force : inout boolean
);
end package;
package body overload_feature is
procedure overload_feature_exec(
variable outcome : inout boolean;
signal rand_ctr :inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 :inout Avalon_mem_type;
signal mem_bus_2 :inout Avalon_mem_type;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal bus_level :in std_logic;
signal drv_bus_1 :in std_logic_vector(1023 downto 0);
signal drv_bus_2 :in std_logic_vector(1023 downto 0);
signal stat_bus_1 :in std_logic_vector(511 downto 0);
signal stat_bus_2 :in std_logic_vector(511 downto 0);
signal bl_inject :inout std_logic;
signal bl_force :inout boolean
)is
variable r_data : std_logic_vector(31 downto 0):=(OTHERS => '0');
variable CAN_frame : SW_CAN_frame_type;
variable frame_sent : boolean:=false;
variable ctr_1 : natural;
variable ctr_2 : natural;
variable ID_1 : natural:=1;
variable ID_2 : natural:=2;
variable rand_val : real;
variable retr_th : natural;
variable mode_backup : std_logic_vector(31 downto 0):=(OTHERS => '0');
begin
outcome:=true;
CAN_generate_frame(rand_ctr,CAN_frame);
CAN_send_frame(CAN_frame,1,ID_1,mem_bus_1,frame_sent);
--Wait until intermission field starts
wait until protocol_type'VAL(to_integer(unsigned(stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW))))=
interframe;
-----------------------------------------------
--Inject dominant bit during the intermission
----------------------------------------------
bl_inject<= DOMINANT;
bl_force <= true;
--Wait for change on protocol state
wait until protocol_type'VAL(to_integer(unsigned(stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW)))) /=
interframe;
--Now overload should have started
if (protocol_type'VAL(to_integer(unsigned(stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW)))) /= overload)then
outcome:=false;
end if;
--Read overload from debug register
CAN_read(r_data,DEBUG_REGISTER_ADR,ID_1,mem_bus_1);
if(r_data(PC_OVR_IND)='0')then
outcome:=false;
end if;
bl_inject<= RECESSIVE;
bl_force<=false;
--Wait until intermission field starts
wait until protocol_type'VAL(to_integer(unsigned(stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW))))=
interframe;
-----------------------------------------------
--Inject dominant bit during the intermission
----------------------------------------------
bl_inject<= DOMINANT;
bl_force <= true;
--Wait for change on protocol state
wait until protocol_type'VAL(to_integer(unsigned(stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW)))) /=
interframe;
--Now overload should have started
if (protocol_type'VAL(to_integer(unsigned(stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW)))) /= overload)then
outcome:=false;
end if;
--Read overload from debug register
CAN_read(r_data,DEBUG_REGISTER_ADR,ID_1,mem_bus_1);
if(r_data(11)='0')then
outcome:=false;
end if;
bl_inject <= RECESSIVE;
bl_force <= false;
CAN_wait_frame_sent(ID_1,mem_bus_1);
end procedure;
procedure overload_feature_exec(
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0);
signal bl_inject : inout std_logic;
signal bl_force : inout boolean
) is
variable r_data : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable CAN_frame : SW_CAN_frame_type;
variable frame_sent : boolean := false;
variable ctr_1 : natural;
variable ctr_2 : natural;
variable ID_1 : natural := 1;
variable ID_2 : natural := 2;
variable rand_val : real;
variable retr_th : natural;
variable mode_backup : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
begin
outcome := true;
------------------------------------------------------------------------
-- Generate CAN Frame and start transmission
------------------------------------------------------------------------
CAN_generate_frame(rand_ctr, CAN_frame);
CAN_send_frame(CAN_frame, 1, ID_1, mem_bus_1, frame_sent);
for i in 0 to 3 loop
--------------------------------------------------------------------
-- Wait until intermission field starts
--------------------------------------------------------------------
wait until protocol_type'VAL(to_integer(unsigned(
stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW)))) =
interframe;
--------------------------------------------------------------------
-- Inject dominant bit during the intermission
--------------------------------------------------------------------
bl_inject <= DOMINANT;
bl_force <= true;
--------------------------------------------------------------------
-- Wait for change on protocol state
--------------------------------------------------------------------
wait until protocol_type'VAL(to_integer(unsigned(
stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW)))) /=
interframe;
--------------------------------------------------------------------
-- Check if overload started
--------------------------------------------------------------------
if (protocol_type'VAL(to_integer(unsigned(
stat_bus_1(STAT_PC_STATE_HIGH downto STAT_PC_STATE_LOW)))) /=
overload)
then
report "Overload did not start";
outcome:=false;
end if;
bl_inject <= RECESSIVE;
bl_force <= false;
end loop;
CAN_wait_frame_sent(ID_1,mem_bus_1);
end procedure;
end package body;
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