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CTU CAN FD IP Core
Commit 69cd69b9 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Merge branch '109-extend-pyxact-generator-with-vhdl-access-generation-2' into 'master' 

Resolve "Extend pyxact generator with VHDL access generation"

Closes #109

See merge request illeondr/CAN_FD_IP_Core!173
parents daeaee63 c8d2d725
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        .gitmodules
        View file @ 69cd69b9
        [submodule "scripts/pyXact_generator/ipyxact_parser"]
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        [submodule "pyXact_generator"]
        path = scripts/pyXact_generator
        url = https://github.com/Blebowski/Reg_Map_Gen
        doc/core/#registerMap.lyx# 0 → 100644
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        doc/core/Product_Brief.lyx
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        doc/core/Product_Brief_new.lyx deleted 100644 → 0
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        \pdf_author "Ille Ondrej"
        \pdf_subject "CAN FD IP function"
        \pdf_keywords "CAN, Flexible data rate,"
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        \begin_body
        \begin_layout Chapter*
        \noindent
        CAN FLEXIBLE DATA-RATE IP CORE
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        PRODUCT BRIEF v2.1
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        \begin_layout Left Header
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        \begin_layout Right Header
        \noindent
        Martin Jerabek, Ondrej Ille
        \end_layout
        \begin_layout Section*
        \noindent
        Overview
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        \begin_layout Standard
        \paragraph_spacing single
        CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
        1.0 and ISO CAN FD specification in a light - weight IP Core.
        It is a soft-core IP Core written in VHDL, with no vendor specific libraries
        needed.
        The main target of usage are FPGA applications, and the core RTL is freely
        available under MIT License in
        \color blue
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        name "Gitlab repository of CTU FEE"
        target "https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core"
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        .
        It is optimized for inference of native hardware blocks such as SRAM memories
        and DSP blocks.
        Generic settings achieve high level of flexibility before synthesis.
        \end_layout
        \begin_layout Standard
        \paragraph_spacing single
        The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
        or APB.
        Easy manipulation with the core is achieved by using hardware buffers for
        CAN frames.
        One FIFO RX buffer is available, and 4 TX buffers are available.
        Timestamps can be captured for various events on the CAN bus and transmission
        of CAN frames can be triggered by external timestamp.
        Three Bit filters and one Range filter is available for HW filtration of
        received CAN frames.
        The Core was synthesized in low-end Xilinx and Altera FPGAs with maximal
        operating frequencies above 100 MHz.
        \end_layout
        \begin_layout Standard
        \paragraph_spacing single
        CTU CAN FD also contains a Linux SocketCAN driver.
        The design contains its own testing framework which is based on Vunit test
        framework and simulated via GHDL or Modelsim.
        At the moment the development team of CTU CAN FD is working on ISO conformance
        testing to guarantee proper operation in commercial applications.
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        \begin_layout Section*
        \noindent
        Features
        \end_layout
        \begin_layout Itemize
        \paragraph_spacing other 0.5
        \noindent
        CAN 2.0, CAN FD 1.0 and ISO CAN FD
        \end_layout
        \begin_layout Itemize
        \paragraph_spacing other 0.5
        \noindent
        RTL VHDL
        \end_layout
        \begin_layout Itemize
        \paragraph_spacing other 0.5
        \noindent
        Pre-synthesis configurable features
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        Avalon compatible memory bus, APB
        \end_layout
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        \noindent
        Timestamping and transmission at given time
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        Optional event and error logging
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        \noindent
        Fault confinement state manipulation
        \end_layout
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        \paragraph_spacing other 0.5
        \noindent
        Transceiver delay measurement
        \end_layout
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        \paragraph_spacing other 0.5
        \noindent
        Size of 1700-2300 ALMs (Intel) , 2500 - 3300 LUTs (Xilinx)
        \end_layout
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        \paragraph_spacing other 0.5
        \noindent
        3 500 - 138 000 SRAM memory bits (Intel), 2.5 - 6 BRAMS (Xilinx)
        \end_layout
        \begin_layout Itemize
        \paragraph_spacing other 0.5
        \noindent
        Synchronization output with time quantum
        \end_layout
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        \noindent
        Filtering of received frames
        \end_layout
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        Listen-only mode, Self-test mode, Acknowledge forbidden mode
        \end_layout
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        Up to 14 Mbit in
        \begin_inset Quotes eld
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        Data
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        Bit-Rate (with 100 MHz Core clock)
        \end_layout
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        \paragraph_spacing other 0.5
        \noindent
        Linux SocketCAN driver available
        \end_layout
        \end_body
        \end_document
        doc/core/Progdokum.lyx
        View file @ 69cd69b9
        ......@@ -533,7 +533,7 @@ Ille Ondrej, Martin Jeřábek
        \noindent
        \align center
        \begin_inset Tabular
        <lyxtabular version="3" rows="5" columns="4">
        <lyxtabular version="3" rows="6" columns="4">
        <features tabularvalignment="middle">
        <column alignment="center" valignment="top" width="1.5cm">
        <column alignment="center" valignment="top" width="2cm">
        ......@@ -696,7 +696,7 @@ Updated register map description, external references to generated maps.
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        ......@@ -705,7 +705,7 @@ Updated register map description, external references to generated maps.
        \end_inset
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        <cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
        \begin_inset Text
        \begin_layout Plain Layout
        ......@@ -714,7 +714,7 @@ Martin Jerabek
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        <cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
        \begin_inset Text
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        ......@@ -723,13 +723,52 @@ Martin Jerabek
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        \begin_inset Text
        \begin_layout Plain Layout
        Added Linux driver description
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        \begin_inset Text
        \begin_layout Plain Layout
        2.1.1
        \end_layout
        \end_inset
        </cell>
        <cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
        \begin_inset Text
        \begin_layout Plain Layout
        Ondrej Ille
        \end_layout
        \end_inset
        </cell>
        <cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
        \begin_inset Text
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        12-2018
        \end_layout
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        \begin_inset Text
        \begin_layout Plain Layout
        Added Register map block diagram after re-implementation of registers via
        Register map generator.
        \end_layout
        \end_inset
        </cell>
        </row>
        ......@@ -1182,21 +1221,17 @@ doc/core/registerMap.lyx
        ).
        \end_layout
        \begin_layout Itemize
        RTL Code of Control Registers module and Event Logger Registers module.
        \end_layout
        \begin_layout Standard
        To generate these design materials CTU CAN FD IP Core contains its own IP-XACT
        generator framework (located under
        \begin_inset Quotes eld
        \end_inset
        scripts/pyXact_generator
        \begin_inset Quotes erd
        \end_inset
        ) which extends the implementation of
        generator which can be found at
        \begin_inset CommandInset href
        LatexCommand href
        name "olofk/ipyxact"
        target "https://github.com/olofk/ipyxact"
        name "regmap_gen"
        target "https://github.com/Blebowski/Reg_Map_Gen"
        literal "false"
        \end_inset
        ......@@ -13110,6 +13145,13 @@ name "fig:TXT_Buffer-FSM"
        \end_inset
        \end_layout
        \begin_layout Standard
        \begin_inset Newpage pagebreak
        \end_inset
        \end_layout
        \begin_layout Subsection
        ......@@ -13144,10 +13186,26 @@ canfd_registers
        \begin_layout Standard
        Memory Registers provide an interface between SoC Memory Bus (Avalon or
        APB) and all control and Status signals of CTU CAN FD IP function.
        Address decoder for access to TXT Buffers is implemented in this module.
        Driving bus assignments are implemented in this module.
        Register structure is in described in Chapter:
        APB) and all control and status signals of CTU CAN FD IP function.
        Memory registers consist of two separate modules: Control registers and
        Event Loger Registers.
        Each module is generated by Register map generator Tool which is further
        described in
        \begin_inset Flex URL
        status open
        \begin_layout Plain Layout
        https://github.com/Blebowski/Reg_Map_Gen
        \end_layout
        \end_inset
        .
        Outputs of Register modules are connected to Driving Bus.
        Inputs to Register modules (corresponding to read-only registers) are driven
        from Status Bus.
        Block diagram is shown in
        \begin_inset ERT
        status open
        ......@@ -13155,15 +13213,71 @@ status open
        \backslash
        hyperref[3.
        CAN FD Core memory map]{3.
        CAN FD Core memory map}
        hyperref[fig:Memory_regs-block-diagram]{Figure }
        \end_layout
        \end_inset
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        reference "fig:Memory_regs-block-diagram"
        plural "false"
        caps "false"
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        .
        Frame Format in TXT Buffers and RX Buffer is described in Chapter:
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        lyxscale 20
        scale 70
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        \end_layout
        \begin_layout Plain Layout
        \begin_inset Caption Standard
        \begin_layout Plain Layout
        Memory registers block diagram
        \begin_inset CommandInset label
        LatexCommand label
        name "fig:Memory_regs-block-diagram"
        \end_inset
        \end_layout
        \end_inset
        \end_layout
        \end_inset
        \end_layout
        \begin_layout Standard
        Register structure is in described in Chapter:
        \begin_inset ERT
        status open
        ......@@ -13171,14 +13285,14 @@ status open
        \backslash
        hyperref[4.
        CAN FD frame format]{4.
        CAN FD frame format}
        hyperref[3.
        CAN FD Core memory map]{3.
        CAN FD Core memory map}
        \end_layout
        \end_inset
        .
        \end_layout
        \begin_layout Standard
        ......@@ -20450,7 +20564,7 @@ BRAMs
        \begin_inset Text
        \begin_layout Plain Layout
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        2640
        \end_layout
        \end_inset
        ......@@ -20459,7 +20573,7 @@ BRAMs
        \begin_inset Text
        \begin_layout Plain Layout
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        \end_layout
        \end_inset
        ......@@ -20506,7 +20620,7 @@ BRAMs
        \begin_inset Text
        \begin_layout Plain Layout
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        2741
        \end_layout
        \end_inset
        ......@@ -20515,7 +20629,7 @@ BRAMs
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        1 714
        1625
        \end_layout
        \end_inset
        ......@@ -20562,7 +20676,7 @@ BRAMs
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        \begin_layout Plain Layout
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        ......@@ -20571,7 +20685,7 @@ BRAMs
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        \end_layout
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        ......@@ -20618,7 +20732,7 @@ BRAMs
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        3106
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        ......@@ -20627,7 +20741,7 @@ BRAMs
        \begin_inset Text
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        1905
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        \end_inset
        ......@@ -20674,7 +20788,7 @@ BRAMs
        \begin_inset Text
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        ......@@ -20683,7 +20797,7 @@ BRAMs
        \begin_inset Text
        \begin_layout Plain Layout
        2 004
        1908
        \end_layout
        \end_inset
        ......
        doc/core/registerMap.lyx
        View file @ 69cd69b9
        ......@@ -3895,7 +3895,7 @@ label{COMMAND
        \end_inset
        \end_layout
        \begin_layout Description
        Type: writeOnce
        Type: write-only
        \end_layout
        \begin_layout Description
        Address: 0x5
        ......@@ -4012,19 +4012,19 @@ Reserved\end_layout
        \end_inset
        </cell>
        <cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
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        \begin_layout Plain Layout
        Reserved\end_layout
        TXFCRST\end_layout
        \end_inset
        </cell>
        <cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
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        \begin_inset Text
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        Reserved\end_layout
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        </cell>
        ......@@ -4090,7 +4090,7 @@ Reset value\end_layout
        \begin_inset Text
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        0\end_layout
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        ......@@ -4098,7 +4098,7 @@ Reset value\end_layout
        \begin_inset Text