Commit 69cd69b9 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '109-extend-pyxact-generator-with-vhdl-access-generation-2' into 'master'

Resolve "Extend pyxact generator with VHDL access generation"

Closes #109

See merge request illeondr/CAN_FD_IP_Core!173
parents daeaee63 c8d2d725
Pipeline #5590 passed with stages
in 44 minutes and 23 seconds
[submodule "scripts/pyXact_generator/ipyxact_parser"]
path = scripts/pyXact_generator/ipyxact_parser
url = https://github.com/oille/ipyxact.git
[submodule "pyXact_generator"]
path = scripts/pyXact_generator
url = https://github.com/Blebowski/Reg_Map_Gen
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\pdf_subject "CAN FD IP function"
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\noindent
CAN FLEXIBLE DATA-RATE IP CORE
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PRODUCT BRIEF v2.1
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\noindent
Martin Jerabek, Ondrej Ille
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\noindent
Overview
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\paragraph_spacing single
CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
1.0 and ISO CAN FD specification in a light - weight IP Core.
It is a soft-core IP Core written in VHDL, with no vendor specific libraries
needed.
The main target of usage are FPGA applications, and the core RTL is freely
available under MIT License in
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.
It is optimized for inference of native hardware blocks such as SRAM memories
and DSP blocks.
Generic settings achieve high level of flexibility before synthesis.
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\paragraph_spacing single
The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
or APB.
Easy manipulation with the core is achieved by using hardware buffers for
CAN frames.
One FIFO RX buffer is available, and 4 TX buffers are available.
Timestamps can be captured for various events on the CAN bus and transmission
of CAN frames can be triggered by external timestamp.
Three Bit filters and one Range filter is available for HW filtration of
received CAN frames.
The Core was synthesized in low-end Xilinx and Altera FPGAs with maximal
operating frequencies above 100 MHz.
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\paragraph_spacing single
CTU CAN FD also contains a Linux SocketCAN driver.
The design contains its own testing framework which is based on Vunit test
framework and simulated via GHDL or Modelsim.
At the moment the development team of CTU CAN FD is working on ISO conformance
testing to guarantee proper operation in commercial applications.
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Features
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CAN 2.0, CAN FD 1.0 and ISO CAN FD
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RTL VHDL
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Pre-synthesis configurable features
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\noindent
Avalon compatible memory bus, APB
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Timestamping and transmission at given time
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Optional event and error logging
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Fault confinement state manipulation
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Transceiver delay measurement
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\noindent
Size of 1700-2300 ALMs (Intel) , 2500 - 3300 LUTs (Xilinx)
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\noindent
3 500 - 138 000 SRAM memory bits (Intel), 2.5 - 6 BRAMS (Xilinx)
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\noindent
Synchronization output with time quantum
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Filtering of received frames
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Listen-only mode, Self-test mode, Acknowledge forbidden mode
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Up to 14 Mbit in
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Data
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Bit-Rate (with 100 MHz Core clock)
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Linux SocketCAN driver available
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......@@ -533,7 +533,7 @@ Ille Ondrej, Martin Jeřábek
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......@@ -696,7 +696,7 @@ Updated register map description, external references to generated maps.
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......@@ -705,7 +705,7 @@ Updated register map description, external references to generated maps.
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......@@ -714,7 +714,7 @@ Martin Jerabek
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......@@ -723,13 +723,52 @@ Martin Jerabek
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Added Linux driver description
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2.1.1
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Ondrej Ille
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12-2018
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Added Register map block diagram after re-implementation of registers via
Register map generator.
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......@@ -1182,21 +1221,17 @@ doc/core/registerMap.lyx
).
\end_layout
\begin_layout Itemize
RTL Code of Control Registers module and Event Logger Registers module.
\end_layout
\begin_layout Standard
To generate these design materials CTU CAN FD IP Core contains its own IP-XACT
generator framework (located under
\begin_inset Quotes eld
\end_inset
scripts/pyXact_generator
\begin_inset Quotes erd
\end_inset
) which extends the implementation of
generator which can be found at
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LatexCommand href
name "olofk/ipyxact"
target "https://github.com/olofk/ipyxact"
name "regmap_gen"
target "https://github.com/Blebowski/Reg_Map_Gen"
literal "false"
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......@@ -13110,6 +13145,13 @@ name "fig:TXT_Buffer-FSM"
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......@@ -13144,10 +13186,26 @@ canfd_registers
\begin_layout Standard
Memory Registers provide an interface between SoC Memory Bus (Avalon or
APB) and all control and Status signals of CTU CAN FD IP function.
Address decoder for access to TXT Buffers is implemented in this module.
Driving bus assignments are implemented in this module.
Register structure is in described in Chapter:
APB) and all control and status signals of CTU CAN FD IP function.
Memory registers consist of two separate modules: Control registers and
Event Loger Registers.
Each module is generated by Register map generator Tool which is further
described in
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https://github.com/Blebowski/Reg_Map_Gen
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.
Outputs of Register modules are connected to Driving Bus.
Inputs to Register modules (corresponding to read-only registers) are driven
from Status Bus.
Block diagram is shown in
\begin_inset ERT
status open
......@@ -13155,15 +13213,71 @@ status open
\backslash
hyperref[3.
CAN FD Core memory map]{3.
CAN FD Core memory map}
hyperref[fig:Memory_regs-block-diagram]{Figure }
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caps "false"
noprefix "false"
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Frame Format in TXT Buffers and RX Buffer is described in Chapter:
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Memory registers block diagram
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Register structure is in described in Chapter:
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status open
......@@ -13171,14 +13285,14 @@ status open
\backslash
hyperref[4.
CAN FD frame format]{4.
CAN FD frame format}
hyperref[3.
CAN FD Core memory map]{3.
CAN FD Core memory map}
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.
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......@@ -20450,7 +20564,7 @@ BRAMs
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......@@ -20459,7 +20573,7 @@ BRAMs
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......@@ -20506,7 +20620,7 @@ BRAMs
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......@@ -20515,7 +20629,7 @@ BRAMs
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......@@ -20562,7 +20676,7 @@ BRAMs
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......@@ -20571,7 +20685,7 @@ BRAMs
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1770
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......@@ -20618,7 +20732,7 @@ BRAMs
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3 030
3106
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......@@ -20627,7 +20741,7 @@ BRAMs
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1905
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......@@ -20674,7 +20788,7 @@ BRAMs
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3157
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......@@ -20683,7 +20797,7 @@ BRAMs
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2 004
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......
......@@ -3895,7 +3895,7 @@ label{COMMAND
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Type: writeOnce
Type: write-only
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\begin_layout Description
Address: 0x5
......@@ -4012,19 +4012,19 @@ Reserved\end_layout
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Reserved\end_layout
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......@@ -4090,7 +4090,7 @@ Reset value\end_layout
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......@@ -4098,7 +4098,7 @@ Reset value\end_layout
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