Merge branch '109-extend-pyxact-generator-with-vhdl-access-generation-2' into 'master'

Resolve "Extend pyxact generator with VHDL access generation"

Closes #109

See merge request illeondr/CAN_FD_IP_Core!173

.gitmodules

-[submodule "scripts/pyXact_generator/ipyxact_parser"]
-	path = scripts/pyXact_generator/ipyxact_parser
-	url = https://github.com/oille/ipyxact.git
+[submodule "pyXact_generator"]
+	path = scripts/pyXact_generator
+	url = https://github.com/Blebowski/Reg_Map_Gen

doc/core/Product_Brief_new.lyx

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-\pdf_author "Ille Ondrej"
-\pdf_subject "CAN FD IP function"
-\pdf_keywords "CAN, Flexible data rate,"
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-
-\begin_body
-
-\begin_layout Chapter*
-\noindent
-CAN FLEXIBLE DATA-RATE IP CORE
-\begin_inset Newline newline
-\end_inset
-
-
-\size large
-PRODUCT BRIEF v2.1
-\end_layout
-
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-
-\begin_layout Left Header
-\noindent
-
-\end_layout
-
-\begin_layout Right Header
-\noindent
-Martin Jerabek, Ondrej Ille
-\end_layout
-
-\begin_layout Section*
-\noindent
-Overview
-\end_layout
-
-\begin_layout Standard
-\paragraph_spacing single
-CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
- 1.0 and ISO CAN FD specification in a light - weight IP Core.
- It is a soft-core IP Core written in VHDL, with no vendor specific libraries
- needed.
- The main target of usage are FPGA applications, and the core RTL is freely
- available under MIT License in 
-\color blue
-
-\begin_inset CommandInset href
-LatexCommand href
-name "Gitlab repository of CTU FEE"
-target "https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core"
-literal "false"
-
-\end_inset
-
-
-\color inherit
-.
- It is optimized for inference of native hardware blocks such as SRAM memories
- and DSP blocks.
- Generic settings achieve high level of flexibility before synthesis.
-\end_layout
-
-\begin_layout Standard
-\paragraph_spacing single
-The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
- or APB.
- Easy manipulation with the core is achieved by using hardware buffers for
- CAN frames.
- One FIFO RX buffer is available, and 4 TX buffers are available.
- Timestamps can be captured for various events on the CAN bus and transmission
- of CAN frames can be triggered by external timestamp.
- Three Bit filters and one Range filter is available for HW filtration of
- received CAN frames.
- The Core was synthesized in low-end Xilinx and Altera FPGAs with maximal
- operating frequencies above 100 MHz.
-\end_layout
-
-\begin_layout Standard
-\paragraph_spacing single
-CTU CAN FD also contains a Linux SocketCAN driver.
- The design contains its own testing framework which is based on Vunit test
- framework and simulated via GHDL or Modelsim.
- At the moment the development team of CTU CAN FD is working on ISO conformance
- testing to guarantee proper operation in commercial applications.
-\end_layout
-
-\begin_layout Standard
-\begin_inset VSpace bigskip
-\end_inset
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-
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-\begin_inset Float figure
-placement h
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-
-\begin_layout Plain Layout
-\noindent
-\align center
-\begin_inset Graphics
-	filename ../pics/Visio_generated/IP_core_block_diagram.pdf
-	lyxscale 10
-	scale 55
-
-\end_inset
-
-
-\end_layout
-
-\end_inset
-
-
-\end_layout
-
-\begin_layout Section*
-\noindent
-Features
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-CAN 2.0, CAN FD 1.0 and ISO CAN FD
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-RTL VHDL
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Pre-synthesis configurable features
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Avalon compatible memory bus, APB
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Timestamping and transmission at given time
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Optional event and error logging
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Fault confinement state manipulation
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Transceiver delay measurement
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Size of 1700-2300 ALMs (Intel) , 2500 - 3300 LUTs (Xilinx) 
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-3 500 - 138 000 SRAM memory bits (Intel), 2.5 - 6 BRAMS (Xilinx) 
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Synchronization output with time quantum
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Filtering of received frames
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Listen-only mode, Self-test mode, Acknowledge forbidden mode
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Up to 14 Mbit in 
-\begin_inset Quotes eld
-\end_inset
-
-Data
-\begin_inset Quotes erd
-\end_inset
-
- Bit-Rate (with 100 MHz Core clock)
-\end_layout
-
-\begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Linux SocketCAN driver available
-\end_layout
-
-\end_body
-\end_document

doc/core/Progdokum.lyx

@@ -533,7 +533,7 @@ Ille Ondrej, Martin Jeřábek
 \noindent
 \align center
 \begin_inset Tabular
-<lyxtabular version="3" rows="5" columns="4">
+<lyxtabular version="3" rows="6" columns="4">
 <features tabularvalignment="middle">
 <column alignment="center" valignment="top" width="1.5cm">
 <column alignment="center" valignment="top" width="2cm">
@@ -696,7 +696,7 @@ Updated register map description, external references to generated maps.
 </cell>
 </row>
 <row>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -705,7 +705,7 @@ Updated register map description, external references to generated maps.
 
 \end_inset
 </cell>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -714,7 +714,7 @@ Martin Jerabek
 
 \end_inset
 </cell>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
@@ -723,13 +723,52 @@ Martin Jerabek
 
 \end_inset
 </cell>
-<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
+<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
 \begin_inset Text
 
 \begin_layout Plain Layout
 Added Linux driver description
 \end_layout
 
+\end_inset
+</cell>
+</row>
+<row>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+2.1.1
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+Ondrej Ille
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+12-2018
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" rightline="true" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+Added Register map block diagram after re-implementation of registers via
+ Register map generator.
+\end_layout
+
 \end_inset
 </cell>
 </row>
@@ -1182,21 +1221,17 @@ doc/core/registerMap.lyx
 ).
 \end_layout
 
+\begin_layout Itemize
+RTL Code of Control Registers module and Event Logger Registers module.
+\end_layout
+
 \begin_layout Standard
 To generate these design materials CTU CAN FD IP Core contains its own IP-XACT
- generator framework (located under 
-\begin_inset Quotes eld
-\end_inset
-
-scripts/pyXact_generator
-\begin_inset Quotes erd
-\end_inset
-
-) which extends the implementation of 
+ generator which can be found at 
 \begin_inset CommandInset href
 LatexCommand href
-name "olofk/ipyxact"
-target "https://github.com/olofk/ipyxact"
+name "regmap_gen"
+target "https://github.com/Blebowski/Reg_Map_Gen"
 literal "false"
 
 \end_inset
@@ -13110,6 +13145,13 @@ name "fig:TXT_Buffer-FSM"
 \end_inset
 
 
+\end_layout
+
+\begin_layout Standard
+\begin_inset Newpage pagebreak
+\end_inset
+
+
 \end_layout
 
 \begin_layout Subsection
@@ -13144,10 +13186,26 @@ canfd_registers
 
 \begin_layout Standard
 Memory Registers provide an interface between SoC Memory Bus (Avalon or
- APB) and all control and Status signals of CTU CAN FD IP function.
- Address decoder for access to TXT Buffers is implemented in this module.
- Driving bus assignments are implemented in this module.
- Register structure is in described in Chapter: 
+ APB) and all control and status signals of CTU CAN FD IP function.
+ Memory registers consist of two separate modules: Control registers and
+ Event Loger Registers.
+ Each module is generated by Register map generator Tool which is further
+ described in 
+\begin_inset Flex URL
+status open
+
+\begin_layout Plain Layout
+
+https://github.com/Blebowski/Reg_Map_Gen
+\end_layout
+
+\end_inset
+
+.
+ Outputs of Register modules are connected to Driving Bus.
+ Inputs to Register modules (corresponding to read-only registers) are driven
+ from Status Bus.
+ Block diagram is shown in 
 \begin_inset ERT
 status open
 
@@ -13155,15 +13213,71 @@ status open
 
 
 \backslash
-hyperref[3.
- CAN FD Core memory map]{3.
- CAN FD Core memory map}
+hyperref[fig:Memory_regs-block-diagram]{Figure }
 \end_layout
 
 \end_inset
 
+ 
+\begin_inset CommandInset ref
+LatexCommand ref
+reference "fig:Memory_regs-block-diagram"
+plural "false"
+caps "false"
+noprefix "false"
+
+\end_inset
+
 .
- Frame Format in TXT Buffers and RX Buffer is described in Chapter: 
+ 
+\end_layout
+
+\begin_layout Standard
+\begin_inset Float figure
+placement h
+wide false
+sideways false
+status open
+
+\begin_layout Plain Layout
+\noindent
+\align center
+\begin_inset Graphics
+	filename ../pics/Visio_generated/Memory_regs_block_diagram.pdf
+	lyxscale 20
+	scale 70
+
+\end_inset
+
+
+\end_layout
+
+\begin_layout Plain Layout
+\begin_inset Caption Standard
+
+\begin_layout Plain Layout
+Memory registers block diagram 
+\begin_inset CommandInset label
+LatexCommand label
+name "fig:Memory_regs-block-diagram"
+
+\end_inset
+
+
+\end_layout
+
+\end_inset
+
+
+\end_layout
+
+\end_inset
+
+
+\end_layout
+
+\begin_layout Standard
+Register structure is in described in Chapter: 
 \begin_inset ERT
 status open
 
@@ -13171,14 +13285,14 @@ status open
 
 
 \backslash
-hyperref[4.
- CAN FD frame format]{4.
- CAN FD frame format}
+hyperref[3.
+ CAN FD Core memory map]{3.
+ CAN FD Core memory map}
 \end_layout
 
 \end_inset
 
-
+.
 \end_layout
 
 \begin_layout Standard
@@ -20450,7 +20564,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-2 500
+2640
 \end_layout
 
 \end_inset
@@ -20459,7 +20573,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-1 569
+1489
 \end_layout
 
 \end_inset
@@ -20506,7 +20620,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-2 661
+2741
 \end_layout
 
 \end_inset
@@ -20515,7 +20629,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-1 714
+1625
 \end_layout
 
 \end_inset
@@ -20562,7 +20676,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-2 819
+2834
 \end_layout
 
 \end_inset
@@ -20571,7 +20685,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-1 867
+1770
 \end_layout
 
 \end_inset
@@ -20618,7 +20732,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-3 030
+3106
 \end_layout
 
 \end_inset
@@ -20627,7 +20741,7 @@ BRAMs
 \begin_inset Text
 
 \begin_layout Plain Layout
-1 942