Merge branch '109-extend-pyxact-generator-with-vhdl-access-generation-2' into 'master'

Resolve "Extend pyxact generator with VHDL access generation"

Closes #109

See merge request illeondr/CAN_FD_IP_Core!173

.gitmodules

-[submodule "scripts/pyXact_generator/ipyxact_parser"]
-	path = scripts/pyXact_generator/ipyxact_parser
-	url = https://github.com/oille/ipyxact.git
+[submodule "pyXact_generator"]
+	path = scripts/pyXact_generator
+	url = https://github.com/Blebowski/Reg_Map_Gen

doc/core/Product_Brief.lyx

-#LyX 2.3 created this file. For more info see http://www.lyx.org/
-\lyxformat 544
+#LyX 2.2 created this file. For more info see http://www.lyx.org/
+\lyxformat 508
 \begin_document
 \begin_header
 \save_transient_properties true
 \origin unavailable
-\textclass achemso
+\textclass IEEEtran
 \begin_preamble
 \usepackage{fancyhdr}
 \renewcommand{\headrulewidth}{0pt}
 \end_preamble
 \use_default_options true
 \begin_modules
-theorems-ams
 eqs-within-sections
 figs-within-sections
 customHeadersFooters
@@ -31,8 +30,6 @@ customHeadersFooters
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 \font_sf_scale 100 100
 \font_tt_scale 100 100
-\use_microtype false
-\use_dash_ligatures true
 \graphics default
 \default_output_format default
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@@ -62,7 +59,6 @@ customHeadersFooters
 \suppress_date false
 \justification true
 \use_refstyle 1
-\use_minted 0
 \index Index
 \shortcut idx
 \color #008000
@@ -71,10 +67,7 @@ customHeadersFooters
 \tocdepth 3
 \paragraph_separation indent
 \paragraph_indentation default
-\is_math_indent 0
-\math_numbering_side default
-\quotes_style english
-\dynamic_quotes 0
+\quotes_language english
 \papercolumns 1
 \papersides 1
 \paperpagestyle default
@@ -88,8 +81,18 @@ customHeadersFooters
 \begin_body
 
 \begin_layout Title
-\noindent
-CAN FD DATA-RATE IP CORE
+\begin_inset space ~
+\end_inset
+
+
+\begin_inset Newline newline
+\end_inset
+
+CAN FLEXIBLE DATA-RATE
+\begin_inset Newline newline
+\end_inset
+
+IP CORE
 \begin_inset Newline newline
 \end_inset
 
@@ -98,12 +101,7 @@ CAN FD DATA-RATE IP CORE
 PRODUCT BRIEF
 \end_layout
 
-\begin_layout Email
-martin.jerabek01@gmail.com, ondrej.ille@gmail.com
-\end_layout
-
 \begin_layout Standard
-\noindent
 \begin_inset ERT
 status open
 
@@ -117,33 +115,132 @@ thispagestyle{fancy}
 \end_inset
 
 
+\end_layout
+
+\begin_layout Left Header
+\begin_inset Tabular
+<lyxtabular version="3" rows="3" columns="2">
+<features tabularvalignment="middle">
+<column alignment="center" valignment="top" width="0pt">
+<column alignment="left" valignment="top" width="0pt">
+<row>
+<cell multirow="3" alignment="left" valignment="middle" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+\begin_inset Graphics
+	filename E:/Skola/CVUT-FEL/LEV.bmp
+	scale 14
+
+\end_inset
+
+
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="left" valignment="top" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+
+\series bold
+Czech Technical University in Prague
+\end_layout
+
+\end_inset
+</cell>
+</row>
+<row>
+<cell multirow="4" alignment="center" valignment="top" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="left" valignment="top" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+Faculty of electrical engineering 
+\end_layout
+
+\end_inset
+</cell>
+</row>
+<row>
+<cell multirow="4" alignment="center" valignment="top" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+
+\end_layout
+
+\end_inset
+</cell>
+<cell alignment="left" valignment="top" usebox="none">
+\begin_inset Text
+
+\begin_layout Plain Layout
+Department of measurement
+\end_layout
+
+\end_inset
+</cell>
+</row>
+</lyxtabular>
+
+\end_inset
+
+
 \end_layout
 
 \begin_layout Right Header
-\noindent
-Martin Jerabek, Ondrej Ille
+Ondrej Ille
 \begin_inset Newline newline
 \end_inset
 
-October 2018
+August 2016
 \end_layout
 
 \begin_layout Section*
-\noindent
 Overview
 \end_layout
 
 \begin_layout Standard
-\paragraph_spacing single
 CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
- 1.0 and ISO CAN FD specification in a light - weight IP Core.
- It is a soft-core IP Core written in VHDL, with no vendor specific libraries
+ 1.0 and ISO CAN FD specification in single light-weight IP Core.
+ It is soft-core IP Core written in VHDL with only standard IEEE libraries
  needed.
- The main target of usage are FPGA applications, and the core RTL is available
- under MIT License in Gitlab repository of CTU FEE.
+ The main target of usage are FPGA applications and the core is available
+ as RTL.
  It is optimized for inference of native hardware blocks such as SRAM memories
- and DSP blocks.
- Generic settings achieve high level of flexibility before synthesis.
+ and multipliers in DSP blocks.
+ Generic settings achieve a high level of flexibility before synthesis.
+ It is posible to balance the core between high amount of features and small
+ size.
+\end_layout
+
+\begin_layout Standard
+The IP Core is accessed as memory mapped peripheria via Avalon bus.
+ Easy manipulation with the core is achieved by using hardware buffers for
+ CAN frames.
+ One FIFO like RX buffer is available and two TX buffers are available.
+ Timestamps can be captured for various events on the CAN bus.
+ Additionally transmission of CAN frames can be triggered by external timestamp.
+ Asynchronous access is supported via rich interrupt settings.
+ Three Bit filters and one Range filter is available on received frames.
+\end_layout
+
+\begin_layout Standard
+The design is fully tested at RTL level as well as in real hardware with
+ Altera Cyclone IV FPGA series.
+ The automated test-framework in TCL is available within the core and it
+ provides an easy way of reproducing unit test, feature covering tests and
+ real bus simulation.
 \end_layout
 
 \begin_layout Standard
@@ -154,9 +251,8 @@ CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
 \end_layout
 
 \begin_layout Standard
-\noindent
 \begin_inset Float figure
-placement h
+placement H
 wide false
 sideways false
 status open
@@ -164,8 +260,88 @@ status open
 \begin_layout Plain Layout
 \noindent
 \align center
+\begin_inset space ~
+\end_inset
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+
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+
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+
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+
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+
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+
+\begin_inset space ~
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+
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+
+\begin_inset space ~
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+
+\begin_inset space ~
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+
+\begin_inset space ~
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+
+
+\begin_inset space ~
+\end_inset
+
+
+\begin_inset space ~
+\end_inset
+
+
+\begin_inset space ~
+\end_inset
+
+
 \begin_inset Graphics
-	filename ../pics/Visio_generated/IP_core_block_diagram.pdf
+	filename E:/Skola/CVUT-FEL/Testovaci Platforma/Obrazky/IP_core_linkedin.jpg
 	lyxscale 10
 	scale 55
 
@@ -179,116 +355,86 @@ status open
 
 \end_layout
 
-\begin_layout Standard
-\paragraph_spacing single
-The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
- or APB.
- Easy manipulation with the core is achieved by using hardware buffers for
- CAN frames.
- One FIFO RX buffer is available, and 4 TX buffers are available.
- Timestamps can be captured for various events on the CAN bus and transmission
- of CAN frames can be triggered by external timestamp.
- Three Bit filters and one Range filter is available for HW filtration of
- received CAN frames.
- The Core was synthesized in Xilinx and Altera FPGAs with approximate maximal
- operating frequency of 100 MHz.
-\end_layout
-
-\begin_layout Standard
-\paragraph_spacing single
-CTU CAN FD also contains a Linux SocketCAN driver.
- The design contains its own testing framework which is based on Vunit test
- framework and simulated via GHDL or Modelsim.
- At the moment the development team of CTU CAN FD is working on ISO conformance
- testing to guarantee proper operation in commercial applications.
-\end_layout
-
 \begin_layout Section*
-\noindent
 Features
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
 CAN 2.0, CAN FD 1.0 and ISO CAN FD
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-RTL VHDL
+\paragraph_spacing onehalf
+RTL VHDL (synthesis), TCL (testing)
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
 Pre-synthesis configurable features
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Avalon compatible memory bus, APB
+\paragraph_spacing onehalf
+Avalon memory bus
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
 Timestamping and transmission at given time
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
 Optional event and error logging
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
 Fault confinement state manipulation
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
 Transceiver delay measurement
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Size of 1700-2300 ALMs (Intel) , 2500 - 3300 LUTs (Xilinx) 
+\paragraph_spacing onehalf
+Size 6 000 - 11 000 LUTs
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-3 500 - 138 000 SRAM memory bits (Intel), 2.5 - 6 BRAMS (Xilinx) 
+\paragraph_spacing onehalf
+2 000 - 12 000 SRAM memory bits
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
 Synchronization output with time quantum
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Filtering of received frames
+\paragraph_spacing onehalf
+Variety of interrupt sources
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Listen-only mode, Self-test mode, Acknowledge forbidden mode
+\paragraph_spacing onehalf
+Filtering of received frame
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
+\paragraph_spacing onehalf
+Listen-only mode, Self-test mode, 
+\begin_inset Newline newline
+\end_inset
+
+Acknowledge forbidden mode
+\end_layout
+
+\begin_layout Itemize
+\paragraph_spacing onehalf
 Up to 14 Mbit in 
 \begin_inset Quotes eld
 \end_inset
@@ -297,13 +443,16 @@ Data
 \begin_inset Quotes erd
 \end_inset
 
- Bit-Rate (with 100 MHz Core clock)
+ bit-rate
+\begin_inset Newline newline
+\end_inset
+
+ (with 100 Mhz Core clock)
 \end_layout
 
 \begin_layout Itemize
-\paragraph_spacing other 0.5
-\noindent
-Linux SocketCAN driver available
+\paragraph_spacing onehalf
+Driver in C available
 \end_layout
 
 \end_body

doc/core/Product_Brief_new.lyx

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-CAN FLEXIBLE DATA-RATE IP CORE
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-PRODUCT BRIEF v2.1
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