Commit 686421b4 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Removed definition of the "memory" type registers

from the kernel header file
parent a9f678aa
......@@ -901,102 +901,6 @@ union yolo_reg {
} s;
};
union txtb1_data_1 {
uint32_t u32;
struct txtb1_data_1_s {
/* TXTB1_DATA_1 */
uint32_t txtb1_data_1 : 32;
} s;
};
union txtb1_data_2 {
uint32_t u32;
struct txtb1_data_2_s {
/* TXTB1_DATA_2 */
uint32_t txtb1_data_2 : 32;
} s;
};
union txtb1_data_20 {
uint32_t u32;
struct txtb1_data_20_s {
/* TXTB1_DATA_20 */
uint32_t txtb1_data_20 : 32;
} s;
};
union txtb2_data_1 {
uint32_t u32;
struct txtb2_data_1_s {
/* TXTB2_DATA_1 */
uint32_t txtb2_data_1 : 32;
} s;
};
union txtb2_data_2 {
uint32_t u32;
struct txtb2_data_2_s {
/* TXTB2_DATA_2 */
uint32_t txtb2_data_2 : 32;
} s;
};
union txtb2_data_20 {
uint32_t u32;
struct txtb2_data_20_s {
/* TXTB2_DATA_20 */
uint32_t txtb2_data_20 : 32;
} s;
};
union txtb3_data_1 {
uint32_t u32;
struct txtb3_data_1_s {
/* TXTB3_DATA_1 */
uint32_t txtb3_data_1 : 32;
} s;
};
union txtb3_data_2 {
uint32_t u32;
struct txtb3_data_2_s {
/* TXTB3_DATA_2 */
uint32_t txtb3_data_2 : 32;
} s;
};
union txtb3_data_20 {
uint32_t u32;
struct txtb3_data_20_s {
/* TXTB3_DATA_20 */
uint32_t txtb3_data_20 : 32;
} s;
};
union txtb4_data_1 {
uint32_t u32;
struct txtb4_data_1_s {
/* TXTB4_DATA_1 */
uint32_t txtb4_data_1 : 32;
} s;
};
union txtb4_data_2 {
uint32_t u32;
struct txtb4_data_2_s {
/* TXTB4_DATA_2 */
uint32_t txtb4_data_2 : 32;
} s;
};
union txtb4_data_20 {
uint32_t u32;
struct txtb4_data_20_s {
/* TXTB4_DATA_20 */
uint32_t txtb4_data_20 : 32;
} s;
};
union log_trig_config {
uint32_t u32;
struct log_trig_config_s {
......
......@@ -104,9 +104,13 @@ class HeaderAddrGenerator(IpXactAddrGenerator):
self.write_reg_enums(reg)
def write_mem_map_fields(self):
for block in self.fieldMap.addressBlock:
# Skip memory blocks.
if (block.usage == "memory"):
continue
self.write_regs(block.register)
......
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