Commit 63e1862d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Updated components for TX arbitrator and TXT Buffer changes.

parent bde7ff98
......@@ -221,21 +221,26 @@ package CANcomponents is
-- TXT Buffer module
------------------------------------------------------------------------------
component txtBuffer is
generic(
constant ID : natural := 1
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal drv_bus : in std_logic_vector(1023 downto 0);
signal tran_data : in std_logic_vector(31 downto 0);
signal tran_addr : in std_logic_vector(4 downto 0);
signal txt_empty : out std_logic;
signal txt_data_ack : in std_logic;
signal txt_data_word : out std_logic_vector(31 downto 0);
signal txt_data_addr : in natural range 0 to 15
);
generic(
constant buf_count : natural range 1 to 8;
constant ID : natural :=1
);
PORT(
signal clk_sys :in std_logic;
signal res_n :in std_logic; --Async reset
signal drv_bus :in std_logic_vector(1023 downto 0);
signal tran_data :in std_logic_vector(31 downto 0);
signal tran_addr :in std_logic_vector(4 downto 0);
signal txt_sw_cmd :in txt_sw_cmd_type;
signal txt_sw_buf_cmd_index :in std_logic_vector(
buf_count - 1 downto 0);
signal txtb_state :out txt_fsm_type;
signal txt_hw_cmd :in txt_hw_cmd_type;
signal txt_hw_cmd_buf_index :in natural range 0 to buf_count - 1;
signal txt_data_word :out std_logic_vector(31 downto 0);
signal txt_data_addr :in natural range 0 to 15;
signal txt_frame_info_out :out std_logic_vector(639 downto 512)
);
end component;
------------------------------------------------------------------------------
......@@ -243,28 +248,29 @@ package CANcomponents is
------------------------------------------------------------------------------
component txArbitrator is
generic(
buf_count : natural range 1 to 8;
tx_time_sup : boolean := true
buf_count : natural range 1 to 8;
tx_time_sup : boolean := true
);
port(
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal txt_buf_data_in :in txtb_data_type;
signal txt_meta_data_in :in txtb_meta_data_type;
signal txt_buf_ready :in std_logic_vector(buf_count - 1 downto 0);
signal tran_data_word_out :out std_logic_vector(31 downto 0);
signal tran_ident_out :out std_logic_vector(28 downto 0);
signal tran_dlc_out :out std_logic_vector(3 downto 0);
signal tran_is_rtr :out std_logic;
signal tran_ident_type_out :out std_logic;
signal tran_frame_type_out :out std_logic;
signal tran_brs_out :out std_logic;
signal tran_frame_valid_out :out std_logic;
signal txt_hw_cmd :in txt_hw_cmd_type;
signal txtb_changed :out std_logic;
signal drv_bus :in std_logic_vector(1023 downto 0);
signal txt_buf_prio :in txtb_priorities_type;
signal timestamp :in std_logic_vector(63 downto 0)
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal txt_buf_data_in :in txtb_data_type;
signal txt_meta_data_in :in txtb_meta_data_type;
signal txt_buf_ready :in std_logic_vector(buf_count - 1 downto 0);
signal tran_data_word_out :out std_logic_vector(31 downto 0);
signal tran_ident_out :out std_logic_vector(28 downto 0);
signal tran_dlc_out :out std_logic_vector(3 downto 0);
signal tran_is_rtr :out std_logic;
signal tran_ident_type_out :out std_logic;
signal tran_frame_type_out :out std_logic;
signal tran_brs_out :out std_logic;
signal tran_frame_valid_out :out std_logic;
signal txt_hw_cmd :in txt_hw_cmd_type;
signal txtb_changed :out std_logic;
signal txt_hw_cmd_buf_index :out natural range 0 to buf_count - 1;
signal drv_bus :in std_logic_vector(1023 downto 0);
signal txt_buf_prio :in txtb_priorities_type;
signal timestamp :in std_logic_vector(63 downto 0)
);
end component;
......
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