Commit 63bb3aa0 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: re-generate vivado component.

parent 023aa760
Pipeline #6554 passed with stages
in 11 minutes and 34 seconds
......@@ -542,6 +542,12 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bit_error_detector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bus_sampling.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -554,6 +560,12 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/sample_mux.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/trv_delay_meas.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -913,6 +925,13 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bit_error_detector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/bus_sampling.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -927,6 +946,13 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/sample_mux.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>bus_sampling/trv_delay_meas.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......
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