Merge branch '205-ssp-offset-feature-test' into 'master'

test: Add SSP_CFG feature test!

Closes #205

See merge request !314

src/can_core/protocol_control_fsm.vhd

@@ -1736,7 +1736,10 @@ begin
                     end if;
                 end if;
                 
-                if (drv_can_fd_ena = FDE_DISABLE and rx_data_nbs = RECESSIVE) then
+                if ((drv_can_fd_ena = FDE_DISABLE) or
+                    (tran_frame_type = NORMAL_CAN and is_transmitter = '1'))
+                    and (rx_data_nbs = RECESSIVE)
+                then
                     form_err_i <= '1';
                 end if;
 
@@ -1812,7 +1815,10 @@ begin
                     ssp_reset_i <= '1';
                 end if;
                 
-                if (drv_can_fd_ena = FDE_DISABLE and rx_data_nbs = RECESSIVE) then
+                if ((drv_can_fd_ena = FDE_DISABLE) or
+                    (tran_frame_type = NORMAL_CAN and is_transmitter = '1'))
+                    and (rx_data_nbs = RECESSIVE)
+                then
                     form_err_i <= '1';
                 end if;
 

test/feature/err_capt_arb_bit_feature_tb.vhd

+--------------------------------------------------------------------------------
+-- 
+-- CTU CAN FD IP Core
+-- Copyright (C) 2015-2018
+-- 
+-- Authors:
+--     Ondrej Ille <ondrej.ille@gmail.com>
+--     Martin Jerabek <martin.jerabek01@gmail.com>
+-- 
+-- Project advisors: 
+-- 	Jiri Novak <jnovak@fel.cvut.cz>
+-- 	Pavel Pisa <pisa@cmp.felk.cvut.cz>
+-- 
+-- Department of Measurement         (http://meas.fel.cvut.cz/)
+-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
+-- Czech Technical University        (http://www.cvut.cz/)
+-- 
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this VHDL component and associated documentation files (the "Component"),
+-- to deal in the Component without restriction, including without limitation
+-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
+-- and/or sell copies of the Component, and to permit persons to whom the
+-- Component is furnished to do so, subject to the following conditions:
+-- 
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Component.
+-- 
+-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
+-- IN THE COMPONENT.
+-- 
+-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
+-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
+-- protocol license from Bosch.
+-- 
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-- Purpose:
+--  ERR_CAPT[ERR_POS] = ERC_POS_ARB, bit error feature test. 
+--
+-- Verifies:
+--  1. Detection of bit error in Arbitration field. Value of ERR_CAPT[ERR_POS]
+--     when bit error should have been detected in arbitration field.
+--
+-- Test sequence:
+--  1. Check that ERR_CAPT contains no error (post reset).
+--  2. Generate CAN frame and send it by Node 1. Wait until transmission starts
+--     and wait until arbitration field. Wait for random amount of time until
+--     Dominant bit is sent! Force bus low and wait until sample point. Check
+--     that Error frame is being transmitted. Check value of ERR_CAPT.
+--------------------------------------------------------------------------------
+-- Revision History:
+--    03.02.2020   Created file
+--------------------------------------------------------------------------------
+
+context work.ctu_can_synth_context;
+context work.ctu_can_test_context;
+
+use lib.pkg_feature_exec_dispath.all;
+
+package err_capt_arb_bit_feature is
+    procedure err_capt_arb_bit_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    );
+end package;
+
+
+package body err_capt_arb_bit_feature is
+    procedure err_capt_arb_bit_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    ) is
+        variable rand_value         :       real;
+        variable alc                :       natural;
+
+        -- Some unit lost the arbitration...
+        -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec
+        variable unit_rec           :     natural := 0;
+
+        variable ID_1               :     natural := 1;
+        variable ID_2               :     natural := 2;
+        variable r_data             :     std_logic_vector(31 downto 0) :=
+                                               (OTHERS => '0');
+        -- Generated frames
+        variable frame_1            :     SW_CAN_frame_type;
+        variable frame_2            :     SW_CAN_frame_type;
+        variable frame_rx           :     SW_CAN_frame_type;
+
+        -- Node status
+        variable stat_1             :     SW_status;
+        variable stat_2             :     SW_status;
+
+        variable pc_dbg             :     SW_PC_Debug;
+        
+        variable txt_buf_state      :     SW_TXT_Buffer_state_type;
+        variable rx_buf_info        :     SW_RX_Buffer_info;
+        variable frames_equal       :     boolean := false;        
+
+        variable id_vect            :     std_logic_vector(28 downto 0);
+        variable wait_time          :     natural;
+        
+        variable err_counters_1_1   :     SW_error_counters;
+        variable err_counters_1_2   :     SW_error_counters;
+
+        variable err_counters_2_1   :     SW_error_counters;
+        variable err_counters_2_2   :     SW_error_counters;
+        
+        variable frame_sent         :     boolean;
+        
+        variable err_capt           :     SW_error_capture;
+
+    begin
+
+        -----------------------------------------------------------------------
+        -- 1. Check that ERR_CAPT contains no error (post reset).
+        -----------------------------------------------------------------------
+        info("Step 1");
+        
+        CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
+        check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!");
+        
+        -----------------------------------------------------------------------        
+        --  2. Generate CAN frame and send it by Node 1. Wait until transmission
+        --     starts and wait until arbitration field. Wait for random amount
+        --     of time until Dominant bit is sent! Force bus low and wait until
+        --     sample point. Check that Error frame is being transmitted. Check
+        --     value of ERR_CAPT.
+        -----------------------------------------------------------------------
+        info("Step 2");
+        
+        CAN_generate_frame(rand_ctr, frame_1);
+        frame_1.ident_type := EXTENDED;
+        CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent);
+        CAN_wait_tx_rx_start(true, false, ID_1, mem_bus(1));
+        
+        CAN_wait_pc_state(pc_deb_arbitration, ID_1, mem_bus(1));
+        
+        -- Wait time is adjusted so that we are sure that we will still be in
+        -- arbitration field (of base or extended). After 26 bits, if there are
+        -- all dominant till end of frame, we are sure at least one stuff bit
+        -- will be there!
+        rand_int_v(rand_ctr, 25, wait_time);
+        info ("Waiting for:" & integer'image(wait_time) & " bits!");
+
+        for i in 1 to wait_time loop
+            CAN_wait_sync_seg(iout(1).stat_bus);
+            info("Wait sync");
+            wait for 20 ns;
+        end loop;
+        info("Waiting finished!");
+
+        while (iout(1).can_tx = RECESSIVE) loop
+            CAN_wait_sync_seg(iout(1).stat_bus);
+            wait for 20 ns;
+        end loop;
+        
+        -- Force bus for one bit time
+        force_bus_level(RECESSIVE, so.bl_force, so.bl_inject);
+        CAN_wait_sample_point(iout(1).stat_bus, false);
+        wait for 20 ns; -- To be sure that opposite bit is sampled!
+        release_bus_level(so.bl_force);
+        
+        get_controller_status(stat_1, ID_1, mem_bus(1));
+        check (stat_1.error_transmission, "Error frame is being transmitted!");
+        
+        CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
+        check(err_capt.err_type = can_err_bit, "Bit error detected!");
+        check(err_capt.err_pos = err_pos_arbitration, "Error detected in Arbitration!");
+        
+        CAN_wait_bus_idle(ID_1, mem_bus(1));
+
+        wait for 100 ns;
+
+  end procedure;
+
+end package body;

test/feature/err_capt_crc_bit_feature_tb.vhd

+--------------------------------------------------------------------------------
+-- 
+-- CTU CAN FD IP Core
+-- Copyright (C) 2015-2018
+-- 
+-- Authors:
+--     Ondrej Ille <ondrej.ille@gmail.com>
+--     Martin Jerabek <martin.jerabek01@gmail.com>
+-- 
+-- Project advisors: 
+-- 	Jiri Novak <jnovak@fel.cvut.cz>
+-- 	Pavel Pisa <pisa@cmp.felk.cvut.cz>
+-- 
+-- Department of Measurement         (http://meas.fel.cvut.cz/)
+-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
+-- Czech Technical University        (http://www.cvut.cz/)
+-- 
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this VHDL component and associated documentation files (the "Component"),
+-- to deal in the Component without restriction, including without limitation
+-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
+-- and/or sell copies of the Component, and to permit persons to whom the
+-- Component is furnished to do so, subject to the following conditions:
+-- 
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Component.
+-- 
+-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
+-- IN THE COMPONENT.
+-- 
+-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
+-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
+-- protocol license from Bosch.
+-- 
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-- Purpose:
+--  ERR_CAPT[ERR_POS] = ERC_POS_CRC feature test - bit error.
+--
+-- Verifies:
+--  1. Detection of bit error in CRC field.
+--  2. Value of ERR_CAPT when bit error is detected in CRC field.
+--
+-- Test sequence:
+--  1. Check that ERR_CAPT contains no error (post reset).
+--  2. Generate CAN frame, send it by Node 1. Wait until CRC field. Wait for
+--     random duration of CRC field. Force bus to opposite value as transmitted
+--     bit wait until sample point. Check that error frame is being transmitted.
+--     Check that ERR_CAPT signals bit error in CRC field!
+--------------------------------------------------------------------------------
+-- Revision History:
+--    03.02.2020   Created file
+--------------------------------------------------------------------------------
+
+context work.ctu_can_synth_context;
+context work.ctu_can_test_context;
+
+use lib.pkg_feature_exec_dispath.all;
+
+package err_capt_crc_bit_feature is
+    procedure err_capt_crc_bit_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    );
+end package;
+
+
+package body err_capt_crc_bit_feature is
+    procedure err_capt_crc_bit_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    ) is
+        variable rand_value         :       real;
+        variable alc                :       natural;
+
+        -- Some unit lost the arbitration...
+        -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec
+        variable unit_rec           :     natural := 0;
+
+        variable ID_1               :     natural := 1;
+        variable ID_2               :     natural := 2;
+        variable r_data             :     std_logic_vector(31 downto 0) :=
+                                               (OTHERS => '0');
+        -- Generated frames
+        variable frame_1            :     SW_CAN_frame_type;
+        variable frame_2            :     SW_CAN_frame_type;
+        variable frame_rx           :     SW_CAN_frame_type;
+
+        -- Node status
+        variable stat_1             :     SW_status;
+        variable stat_2             :     SW_status;
+
+        variable pc_dbg             :     SW_PC_Debug;
+        
+        variable txt_buf_state      :     SW_TXT_Buffer_state_type;
+        variable rx_buf_info        :     SW_RX_Buffer_info;
+        variable frames_equal       :     boolean := false;        
+
+        variable id_vect            :     std_logic_vector(28 downto 0);
+        variable wait_time          :     natural;
+        
+        variable err_counters_1_1   :     SW_error_counters;
+        variable err_counters_1_2   :     SW_error_counters;
+
+        variable err_counters_2_1   :     SW_error_counters;
+        variable err_counters_2_2   :     SW_error_counters;
+        
+        variable frame_sent         :     boolean;
+        
+        variable err_capt           :     SW_error_capture;
+        variable tmp                :     natural;
+        variable crc_len            :     natural;
+
+    begin
+
+        -----------------------------------------------------------------------
+        -- 1. Check that ERR_CAPT contains no error (post reset).
+        -----------------------------------------------------------------------
+        info("Step 1");
+
+        CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
+        check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!");
+
+        -----------------------------------------------------------------------
+        -- 2. Generate CAN frame, send it by Node 1. Wait until data field.
+        --    Wait for random duration of data field. Force bus to opposite
+        --    value as transmitted bit wait until sample point. Check that
+        --    error frame is being transmitted. Check that ERR_CAPT signals bit
+        --    error in data field!
+        -----------------------------------------------------------------------
+        info("Step 2");
+
+        CAN_generate_frame(rand_ctr, frame_1);
+        frame_1.rtr := NO_RTR_FRAME;
+        
+        -- Don't sample by SSP!
+        frame_1.brs := BR_NO_SHIFT;
+        
+        CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent);
+        CAN_wait_tx_rx_start(true, false, ID_1, mem_bus(1));
+        
+        if (frame_1.frame_format = FD_CAN) then
+            CAN_wait_pc_state(pc_deb_stuff_count, ID_1, mem_bus(1));
+        else
+            CAN_wait_pc_state(pc_deb_crc, ID_1, mem_bus(1));
+        end if;
+
+        -- Wait for random number of bits
+        if (frame_1.frame_format = FD_CAN) then
+            if (frame_1.data_length > 16) then
+                crc_len := 24; -- CRC21 + Stuff count + Parity - 1
+            else
+                crc_len := 20; -- CRC17 + Stuff count + Parity - 1
+            end if;
+        else
+            crc_len := 15; -- CRC 15 (CAN 2.0 frames have no Stuff count)!
+        end if;
+
+        -- Wait for Random amount of time!
+        rand_int_v(rand_ctr, crc_len - 1, tmp);
+        info("Waiting for: " & integer'image(tmp) & " bits!");
+        for i in 1 to tmp loop
+            CAN_wait_sample_point(iout(1).stat_bus, true);
+        end loop;
+
+        CAN_wait_sync_seg(iout(1).stat_bus);
+        wait for 20 ns;
+
+        force_bus_level(not iout(1).can_tx, so.bl_force, so.bl_inject);
+        CAN_wait_sample_point(iout(1).stat_bus, false);
+        wait for 20 ns; -- To be sure that opposite bit is sampled!
+        release_bus_level(so.bl_force);
+        
+        get_controller_status(stat_1, ID_1, mem_bus(1));
+        check (stat_1.error_transmission, "Error frame is being transmitted!");
+        
+        CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
+        check(err_capt.err_type = can_err_bit, "Bit error detected!");
+        check(err_capt.err_pos = err_pos_crc, "Error detected in CRC field!");
+        
+        CAN_wait_bus_idle(ID_1, mem_bus(1));
+
+        wait for 100 ns;
+
+  end procedure;
+
+end package body;

test/feature/err_capt_ctrl_bit_feature_tb.vhd

+--------------------------------------------------------------------------------
+-- 
+-- CTU CAN FD IP Core
+-- Copyright (C) 2015-2018
+-- 
+-- Authors:
+--     Ondrej Ille <ondrej.ille@gmail.com>
+--     Martin Jerabek <martin.jerabek01@gmail.com>
+-- 
+-- Project advisors: 
+-- 	Jiri Novak <jnovak@fel.cvut.cz>
+-- 	Pavel Pisa <pisa@cmp.felk.cvut.cz>
+-- 
+-- Department of Measurement         (http://meas.fel.cvut.cz/)
+-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
+-- Czech Technical University        (http://www.cvut.cz/)
+-- 
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this VHDL component and associated documentation files (the "Component"),
+-- to deal in the Component without restriction, including without limitation
+-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
+-- and/or sell copies of the Component, and to permit persons to whom the
+-- Component is furnished to do so, subject to the following conditions:
+-- 
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Component.
+-- 
+-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
+-- IN THE COMPONENT.
+-- 
+-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
+-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
+-- protocol license from Bosch.
+-- 
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-- Purpose:
+--  ERR_CAPT[ERR_POS] = ERC_POS_CTRL, bit error feature test. 
+--
+-- Verifies:
+--  1. Detection of bit error in IDE bit of frame with Base identifier!
+--  2. Detection of bit error in EDL bit of CAN FD frame with Base identifier
+--     and with Extended Identifier!
+--  3. Detection of bit error in ESI/BRS and DLC bit fields.
+--  4. Value of ERR_CAPT[ERR_POS] when bit error shall be detected in control
+--     field of CAN frame!
+--
+-- Test sequence:
+--  1. Check that ERR_CAPT contains no error (post reset).
+--  2. Generate CAN frame (frame with Base ID only, CAN FD frames with Base and
+--     extended identifier, CAN FD frame with Base identifier), send it by
+--     Node 1. Wait until Arbitration field and until sample point of one bit
+--     before bit error shall be detected. Force bus to opposite value as shall
+--     be transmitted and wait until sample point. Check that Node is transmitting
+--     error frame. Check that ERR_CAPT signals Bit Error in Control field.
+--     Reset the node, Wait until integration is over and check that ERR_CAPT
+--     is at its reset value (this is to check that next loops will truly set
+--     ERR_CAPT). Repeat with each frame type!
+--------------------------------------------------------------------------------
+-- Revision History:
+--    03.02.2020   Created file
+--------------------------------------------------------------------------------
+
+context work.ctu_can_synth_context;
+context work.ctu_can_test_context;
+
+use lib.pkg_feature_exec_dispath.all;
+
+package err_capt_ctrl_bit_feature is
+    procedure err_capt_ctrl_bit_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    );
+end package;
+
+
+package body err_capt_ctrl_bit_feature is
+    procedure err_capt_ctrl_bit_feature_exec(
+        signal      so              : out    feature_signal_outputs_t;
+        signal      rand_ctr        : inout  natural range 0 to RAND_POOL_SIZE;
+        signal      iout            : in     instance_outputs_arr_t;
+        signal      mem_bus         : inout  mem_bus_arr_t;
+        signal      bus_level       : in     std_logic
+    ) is
+        variable rand_value         :       real;
+        variable alc                :       natural;
+
+        -- Some unit lost the arbitration...
+        -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec
+        variable unit_rec           :     natural := 0;
+
+        variable ID_1               :     natural := 1;
+        variable ID_2               :     natural := 2;
+        variable r_data             :     std_logic_vector(31 downto 0) :=
+                                               (OTHERS => '0');
+        -- Generated frames
+        variable frame_1            :     SW_CAN_frame_type;
+        variable frame_2            :     SW_CAN_frame_type;
+        variable frame_rx           :     SW_CAN_frame_type;
+
+        -- Node status
+        variable stat_1             :     SW_status;
+        variable stat_2             :     SW_status;
+
+        variable pc_dbg             :     SW_PC_Debug;
+        
+        variable txt_buf_state      :     SW_TXT_Buffer_state_type;
+        variable rx_buf_info        :     SW_RX_Buffer_info;
+        variable frames_equal       :     boolean := false;        
+
+        variable id_vect            :     std_logic_vector(28 downto 0);
+        variable wait_time          :     natural;
+        
+        variable err_counters_1_1   :     SW_error_counters;
+        variable err_counters_1_2   :     SW_error_counters;
+
+        variable err_counters_2_1   :     SW_error_counters;
+        variable err_counters_2_2   :     SW_error_counters;
+        
+        variable frame_sent         :     boolean;
+        
+        variable err_capt           :     SW_error_capture;
+        variable tmp                :     natural;
+        
+        variable force_value        :     std_logic := '0';
+
+    begin
+
+        -- Other controller is not need in this test. Disable it not to have
+        -- failing assertions due to force bit errors!
+        CAN_turn_controller(false, ID_2, mem_bus(2));
+
+        -----------------------------------------------------------------------
+        -- 1. Check that ERR_CAPT contains no error (post reset).
+        -----------------------------------------------------------------------
+        info("Step 1");
+        
+        CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
+        check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!");
+        
+        -----------------------------------------------------------------------
+        -- 2. Generate CAN frame (frame with Base ID only, CAN FD frames with
+        --    Base and extended identifier, CAN FD frame with Base identifier),
+        --    send it by Node 1. Wait until Arbitration field and until sample
+        --    point of one bit before bit error shall be detected. Force bus to
+        --    opposite value as shall be transmitted and wait until sample point.
+        --    Check that Node is transmitting error frame. Check that ERR_CAPT
+        --    signals Bit Error in Control field. Reset the node, Wait until
+        --    integration is over and check that ERR_CAPT is at its reset value
+        --    (this is to check that next loops will truly set ERR_CAPT).
+        --    Repeat with each frame type!
+        -----------------------------------------------------------------------
+        for i in 1 to 4 loop
+            info ("Inner Loop: " & integer'image(i));
+            CAN_generate_frame(rand_ctr, frame_1);
+            
+            -- ID is not important in this TC. Avoid overflows of high generated
+            -- IDs on Base IDs!
+            frame_1.identifier := 10;
+            -- This is to avoid failing assertions on simultaneous RTR and EDL
+            -- flag (if r0 is corrupted by TC to be recessive!). RTR flag is
+            -- not important in this TC, therefore we can afford to fixate it!
+            frame_1.RTR := NO_RTR_FRAME;
+            
+            case i is
+            when 1 =>
+                frame_1.ident_type := BASE;
+                wait_time := 12; -- Till IDE
+                force_value := RECESSIVE;
+            when 2 =>
+                frame_1.frame_format := FD_CAN;
+                frame_1.ident_type := BASE;
+                wait_time := 13; -- Till EDL
+                force_value := DOMINANT;
+            when 3 =>
+                frame_1.frame_format := FD_CAN;
+                frame_1.ident_type := EXTENDED;
+                wait_time := 32; -- Till EDL
+                force_value := DOMINANT;
+            when 4 =>
+                frame_1.frame_format := FD_CAN;
+                frame_1.ident_type := BASE;