diff --git a/src/can_core/protocol_control_fsm.vhd b/src/can_core/protocol_control_fsm.vhd index e1c9fc967edd0330f28c854b3c21c2010125b01c..0d2b72e1bad9a2f0c470098eb7563582810fcc6a 100644 --- a/src/can_core/protocol_control_fsm.vhd +++ b/src/can_core/protocol_control_fsm.vhd @@ -1736,7 +1736,10 @@ begin end if; end if; - if (drv_can_fd_ena = FDE_DISABLE and rx_data_nbs = RECESSIVE) then + if ((drv_can_fd_ena = FDE_DISABLE) or + (tran_frame_type = NORMAL_CAN and is_transmitter = '1')) + and (rx_data_nbs = RECESSIVE) + then form_err_i <= '1'; end if; @@ -1812,7 +1815,10 @@ begin ssp_reset_i <= '1'; end if; - if (drv_can_fd_ena = FDE_DISABLE and rx_data_nbs = RECESSIVE) then + if ((drv_can_fd_ena = FDE_DISABLE) or + (tran_frame_type = NORMAL_CAN and is_transmitter = '1')) + and (rx_data_nbs = RECESSIVE) + then form_err_i <= '1'; end if; diff --git a/test/feature/err_capt_arb_bit_feature_tb.vhd b/test/feature/err_capt_arb_bit_feature_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..65aa0d05871c291e67682b54b4437d864f361213 --- /dev/null +++ b/test/feature/err_capt_arb_bit_feature_tb.vhd @@ -0,0 +1,188 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- ERR_CAPT[ERR_POS] = ERC_POS_ARB, bit error feature test. +-- +-- Verifies: +-- 1. Detection of bit error in Arbitration field. Value of ERR_CAPT[ERR_POS] +-- when bit error should have been detected in arbitration field. +-- +-- Test sequence: +-- 1. Check that ERR_CAPT contains no error (post reset). +-- 2. Generate CAN frame and send it by Node 1. Wait until transmission starts +-- and wait until arbitration field. Wait for random amount of time until +-- Dominant bit is sent! Force bus low and wait until sample point. Check +-- that Error frame is being transmitted. Check value of ERR_CAPT. +-------------------------------------------------------------------------------- +-- Revision History: +-- 03.02.2020 Created file +-------------------------------------------------------------------------------- + +context work.ctu_can_synth_context; +context work.ctu_can_test_context; + +use lib.pkg_feature_exec_dispath.all; + +package err_capt_arb_bit_feature is + procedure err_capt_arb_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ); +end package; + + +package body err_capt_arb_bit_feature is + procedure err_capt_arb_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ) is + variable rand_value : real; + variable alc : natural; + + -- Some unit lost the arbitration... + -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec + variable unit_rec : natural := 0; + + variable ID_1 : natural := 1; + variable ID_2 : natural := 2; + variable r_data : std_logic_vector(31 downto 0) := + (OTHERS => '0'); + -- Generated frames + variable frame_1 : SW_CAN_frame_type; + variable frame_2 : SW_CAN_frame_type; + variable frame_rx : SW_CAN_frame_type; + + -- Node status + variable stat_1 : SW_status; + variable stat_2 : SW_status; + + variable pc_dbg : SW_PC_Debug; + + variable txt_buf_state : SW_TXT_Buffer_state_type; + variable rx_buf_info : SW_RX_Buffer_info; + variable frames_equal : boolean := false; + + variable id_vect : std_logic_vector(28 downto 0); + variable wait_time : natural; + + variable err_counters_1_1 : SW_error_counters; + variable err_counters_1_2 : SW_error_counters; + + variable err_counters_2_1 : SW_error_counters; + variable err_counters_2_2 : SW_error_counters; + + variable frame_sent : boolean; + + variable err_capt : SW_error_capture; + + begin + + ----------------------------------------------------------------------- + -- 1. Check that ERR_CAPT contains no error (post reset). + ----------------------------------------------------------------------- + info("Step 1"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!"); + + ----------------------------------------------------------------------- + -- 2. Generate CAN frame and send it by Node 1. Wait until transmission + -- starts and wait until arbitration field. Wait for random amount + -- of time until Dominant bit is sent! Force bus low and wait until + -- sample point. Check that Error frame is being transmitted. Check + -- value of ERR_CAPT. + ----------------------------------------------------------------------- + info("Step 2"); + + CAN_generate_frame(rand_ctr, frame_1); + frame_1.ident_type := EXTENDED; + CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent); + CAN_wait_tx_rx_start(true, false, ID_1, mem_bus(1)); + + CAN_wait_pc_state(pc_deb_arbitration, ID_1, mem_bus(1)); + + -- Wait time is adjusted so that we are sure that we will still be in + -- arbitration field (of base or extended). After 26 bits, if there are + -- all dominant till end of frame, we are sure at least one stuff bit + -- will be there! + rand_int_v(rand_ctr, 25, wait_time); + info ("Waiting for:" & integer'image(wait_time) & " bits!"); + + for i in 1 to wait_time loop + CAN_wait_sync_seg(iout(1).stat_bus); + info("Wait sync"); + wait for 20 ns; + end loop; + info("Waiting finished!"); + + while (iout(1).can_tx = RECESSIVE) loop + CAN_wait_sync_seg(iout(1).stat_bus); + wait for 20 ns; + end loop; + + -- Force bus for one bit time + force_bus_level(RECESSIVE, so.bl_force, so.bl_inject); + CAN_wait_sample_point(iout(1).stat_bus, false); + wait for 20 ns; -- To be sure that opposite bit is sampled! + release_bus_level(so.bl_force); + + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, "Error frame is being transmitted!"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_type = can_err_bit, "Bit error detected!"); + check(err_capt.err_pos = err_pos_arbitration, "Error detected in Arbitration!"); + + CAN_wait_bus_idle(ID_1, mem_bus(1)); + + wait for 100 ns; + + end procedure; + +end package body; diff --git a/test/feature/err_capt_crc_bit_feature_tb.vhd b/test/feature/err_capt_crc_bit_feature_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..76929571190b14d1ef26babe53928978e797f46b --- /dev/null +++ b/test/feature/err_capt_crc_bit_feature_tb.vhd @@ -0,0 +1,199 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- ERR_CAPT[ERR_POS] = ERC_POS_CRC feature test - bit error. +-- +-- Verifies: +-- 1. Detection of bit error in CRC field. +-- 2. Value of ERR_CAPT when bit error is detected in CRC field. +-- +-- Test sequence: +-- 1. Check that ERR_CAPT contains no error (post reset). +-- 2. Generate CAN frame, send it by Node 1. Wait until CRC field. Wait for +-- random duration of CRC field. Force bus to opposite value as transmitted +-- bit wait until sample point. Check that error frame is being transmitted. +-- Check that ERR_CAPT signals bit error in CRC field! +-------------------------------------------------------------------------------- +-- Revision History: +-- 03.02.2020 Created file +-------------------------------------------------------------------------------- + +context work.ctu_can_synth_context; +context work.ctu_can_test_context; + +use lib.pkg_feature_exec_dispath.all; + +package err_capt_crc_bit_feature is + procedure err_capt_crc_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ); +end package; + + +package body err_capt_crc_bit_feature is + procedure err_capt_crc_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ) is + variable rand_value : real; + variable alc : natural; + + -- Some unit lost the arbitration... + -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec + variable unit_rec : natural := 0; + + variable ID_1 : natural := 1; + variable ID_2 : natural := 2; + variable r_data : std_logic_vector(31 downto 0) := + (OTHERS => '0'); + -- Generated frames + variable frame_1 : SW_CAN_frame_type; + variable frame_2 : SW_CAN_frame_type; + variable frame_rx : SW_CAN_frame_type; + + -- Node status + variable stat_1 : SW_status; + variable stat_2 : SW_status; + + variable pc_dbg : SW_PC_Debug; + + variable txt_buf_state : SW_TXT_Buffer_state_type; + variable rx_buf_info : SW_RX_Buffer_info; + variable frames_equal : boolean := false; + + variable id_vect : std_logic_vector(28 downto 0); + variable wait_time : natural; + + variable err_counters_1_1 : SW_error_counters; + variable err_counters_1_2 : SW_error_counters; + + variable err_counters_2_1 : SW_error_counters; + variable err_counters_2_2 : SW_error_counters; + + variable frame_sent : boolean; + + variable err_capt : SW_error_capture; + variable tmp : natural; + variable crc_len : natural; + + begin + + ----------------------------------------------------------------------- + -- 1. Check that ERR_CAPT contains no error (post reset). + ----------------------------------------------------------------------- + info("Step 1"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!"); + + ----------------------------------------------------------------------- + -- 2. Generate CAN frame, send it by Node 1. Wait until data field. + -- Wait for random duration of data field. Force bus to opposite + -- value as transmitted bit wait until sample point. Check that + -- error frame is being transmitted. Check that ERR_CAPT signals bit + -- error in data field! + ----------------------------------------------------------------------- + info("Step 2"); + + CAN_generate_frame(rand_ctr, frame_1); + frame_1.rtr := NO_RTR_FRAME; + + -- Don't sample by SSP! + frame_1.brs := BR_NO_SHIFT; + + CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent); + CAN_wait_tx_rx_start(true, false, ID_1, mem_bus(1)); + + if (frame_1.frame_format = FD_CAN) then + CAN_wait_pc_state(pc_deb_stuff_count, ID_1, mem_bus(1)); + else + CAN_wait_pc_state(pc_deb_crc, ID_1, mem_bus(1)); + end if; + + -- Wait for random number of bits + if (frame_1.frame_format = FD_CAN) then + if (frame_1.data_length > 16) then + crc_len := 24; -- CRC21 + Stuff count + Parity - 1 + else + crc_len := 20; -- CRC17 + Stuff count + Parity - 1 + end if; + else + crc_len := 15; -- CRC 15 (CAN 2.0 frames have no Stuff count)! + end if; + + -- Wait for Random amount of time! + rand_int_v(rand_ctr, crc_len - 1, tmp); + info("Waiting for: " & integer'image(tmp) & " bits!"); + for i in 1 to tmp loop + CAN_wait_sample_point(iout(1).stat_bus, true); + end loop; + + CAN_wait_sync_seg(iout(1).stat_bus); + wait for 20 ns; + + force_bus_level(not iout(1).can_tx, so.bl_force, so.bl_inject); + CAN_wait_sample_point(iout(1).stat_bus, false); + wait for 20 ns; -- To be sure that opposite bit is sampled! + release_bus_level(so.bl_force); + + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, "Error frame is being transmitted!"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_type = can_err_bit, "Bit error detected!"); + check(err_capt.err_pos = err_pos_crc, "Error detected in CRC field!"); + + CAN_wait_bus_idle(ID_1, mem_bus(1)); + + wait for 100 ns; + + end procedure; + +end package body; diff --git a/test/feature/err_capt_ctrl_bit_feature_tb.vhd b/test/feature/err_capt_ctrl_bit_feature_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..6cd3df8ef706f4059c3ec03d8f12381844d4a8ae --- /dev/null +++ b/test/feature/err_capt_ctrl_bit_feature_tb.vhd @@ -0,0 +1,263 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- ERR_CAPT[ERR_POS] = ERC_POS_CTRL, bit error feature test. +-- +-- Verifies: +-- 1. Detection of bit error in IDE bit of frame with Base identifier! +-- 2. Detection of bit error in EDL bit of CAN FD frame with Base identifier +-- and with Extended Identifier! +-- 3. Detection of bit error in ESI/BRS and DLC bit fields. +-- 4. Value of ERR_CAPT[ERR_POS] when bit error shall be detected in control +-- field of CAN frame! +-- +-- Test sequence: +-- 1. Check that ERR_CAPT contains no error (post reset). +-- 2. Generate CAN frame (frame with Base ID only, CAN FD frames with Base and +-- extended identifier, CAN FD frame with Base identifier), send it by +-- Node 1. Wait until Arbitration field and until sample point of one bit +-- before bit error shall be detected. Force bus to opposite value as shall +-- be transmitted and wait until sample point. Check that Node is transmitting +-- error frame. Check that ERR_CAPT signals Bit Error in Control field. +-- Reset the node, Wait until integration is over and check that ERR_CAPT +-- is at its reset value (this is to check that next loops will truly set +-- ERR_CAPT). Repeat with each frame type! +-------------------------------------------------------------------------------- +-- Revision History: +-- 03.02.2020 Created file +-------------------------------------------------------------------------------- + +context work.ctu_can_synth_context; +context work.ctu_can_test_context; + +use lib.pkg_feature_exec_dispath.all; + +package err_capt_ctrl_bit_feature is + procedure err_capt_ctrl_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ); +end package; + + +package body err_capt_ctrl_bit_feature is + procedure err_capt_ctrl_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ) is + variable rand_value : real; + variable alc : natural; + + -- Some unit lost the arbitration... + -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec + variable unit_rec : natural := 0; + + variable ID_1 : natural := 1; + variable ID_2 : natural := 2; + variable r_data : std_logic_vector(31 downto 0) := + (OTHERS => '0'); + -- Generated frames + variable frame_1 : SW_CAN_frame_type; + variable frame_2 : SW_CAN_frame_type; + variable frame_rx : SW_CAN_frame_type; + + -- Node status + variable stat_1 : SW_status; + variable stat_2 : SW_status; + + variable pc_dbg : SW_PC_Debug; + + variable txt_buf_state : SW_TXT_Buffer_state_type; + variable rx_buf_info : SW_RX_Buffer_info; + variable frames_equal : boolean := false; + + variable id_vect : std_logic_vector(28 downto 0); + variable wait_time : natural; + + variable err_counters_1_1 : SW_error_counters; + variable err_counters_1_2 : SW_error_counters; + + variable err_counters_2_1 : SW_error_counters; + variable err_counters_2_2 : SW_error_counters; + + variable frame_sent : boolean; + + variable err_capt : SW_error_capture; + variable tmp : natural; + + variable force_value : std_logic := '0'; + + begin + + -- Other controller is not need in this test. Disable it not to have + -- failing assertions due to force bit errors! + CAN_turn_controller(false, ID_2, mem_bus(2)); + + ----------------------------------------------------------------------- + -- 1. Check that ERR_CAPT contains no error (post reset). + ----------------------------------------------------------------------- + info("Step 1"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!"); + + ----------------------------------------------------------------------- + -- 2. Generate CAN frame (frame with Base ID only, CAN FD frames with + -- Base and extended identifier, CAN FD frame with Base identifier), + -- send it by Node 1. Wait until Arbitration field and until sample + -- point of one bit before bit error shall be detected. Force bus to + -- opposite value as shall be transmitted and wait until sample point. + -- Check that Node is transmitting error frame. Check that ERR_CAPT + -- signals Bit Error in Control field. Reset the node, Wait until + -- integration is over and check that ERR_CAPT is at its reset value + -- (this is to check that next loops will truly set ERR_CAPT). + -- Repeat with each frame type! + ----------------------------------------------------------------------- + for i in 1 to 4 loop + info ("Inner Loop: " & integer'image(i)); + CAN_generate_frame(rand_ctr, frame_1); + + -- ID is not important in this TC. Avoid overflows of high generated + -- IDs on Base IDs! + frame_1.identifier := 10; + -- This is to avoid failing assertions on simultaneous RTR and EDL + -- flag (if r0 is corrupted by TC to be recessive!). RTR flag is + -- not important in this TC, therefore we can afford to fixate it! + frame_1.RTR := NO_RTR_FRAME; + + case i is + when 1 => + frame_1.ident_type := BASE; + wait_time := 12; -- Till IDE + force_value := RECESSIVE; + when 2 => + frame_1.frame_format := FD_CAN; + frame_1.ident_type := BASE; + wait_time := 13; -- Till EDL + force_value := DOMINANT; + when 3 => + frame_1.frame_format := FD_CAN; + frame_1.ident_type := EXTENDED; + wait_time := 32; -- Till EDL + force_value := DOMINANT; + when 4 => + frame_1.frame_format := FD_CAN; + frame_1.ident_type := BASE; + wait_time := 15; -- Till r0 + + -- Extend wait time to random BRS,ESI or DLC + rand_int_v(rand_ctr, 5, tmp); + wait_time := wait_time + tmp; + + -- Force value: + -- BRS -> Opposite of BRS + -- ESI -> Recessive (we are error active so we transmit dominabt) + -- DLC -> opposite of n-th bit of DLC! + case tmp is + when 0 => + force_value := not frame_1.brs; + info("Forcing BRS to dominant!"); + when 1 => + force_value := RECESSIVE; + info("Forcing ESI to recessive!"); + when 2 => + force_value := not frame_1.dlc(3); + info("Forcing DLC(3)"); + when 3 => + force_value := not frame_1.dlc(2); + info("Forcing DLC(2)"); + when 4 => + force_value := not frame_1.dlc(1); + info("Forcing DLC(1)"); + when 5 => + force_value := not frame_1.dlc(0); + info("Forcing DLC(0)"); + when others => + error("Invalid generated number!"); + end case; + end case; + + CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent); + CAN_wait_pc_state(pc_deb_arbitration, ID_1, mem_bus(1)); + + info("Waiting for: " & integer'image(wait_time) & " bits!"); + for j in 1 to wait_time loop + CAN_wait_sample_point(iout(1).stat_bus, true); + end loop; + + -- Force bus for one bit time + force_bus_level(force_value, so.bl_force, so.bl_inject); + CAN_wait_sample_point(iout(1).stat_bus, false); + wait for 20 ns; -- To be sure that opposite bit is sampled! + release_bus_level(so.bl_force); + + -- Check errors + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, + "Error frame is being transmitted!"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_type = can_err_bit, "Bit error detected!"); + check(err_capt.err_pos = err_pos_ctrl, + "Error detected in Control field!"); + wait for 100 ns; -- For debug only to see waves properly! + + -- Reset the node + exec_SW_reset(ID_1, mem_bus(1)); + CAN_turn_controller(true, ID_1, mem_bus(1)); + CAN_wait_bus_on(ID_1, mem_bus(1)); + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_pos = err_pos_other, "Reset value other"); + end loop; + + wait for 100 ns; + + end procedure; + +end package body; diff --git a/test/feature/err_capt_ctrl_form_feature_tb.vhd b/test/feature/err_capt_ctrl_form_feature_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..95cdaae5f276811c6782831d4989f53831e721b3 --- /dev/null +++ b/test/feature/err_capt_ctrl_form_feature_tb.vhd @@ -0,0 +1,229 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- ERR_CAPT[ERR_POS] = ERC_POS_CTRL, form error feature test. +-- +-- Verifies: +-- 1. Detection of form error in control field on r0 bit in CAN 2.0 base frame, +-- on r0 bit in CAN FD base frame, on r0/r1 bits in CAN 2.0 extended frame +-- and r0 in CAN FD extended frame! +-- 2. Value of ERR_CAPT[ERR_POS] when form error shall be detected in control +-- field of CAN frame! +-- +-- Test sequence: +-- 1. Check that ERR_CAPT contains no error (post reset). +-- 2. Generate CAN frame (CAN 2.0 Base only, CAN FD Base only, CAN 2.0 Extended, +-- CAN FD extended), send it by Node 1. Wait until Arbitration field and wait +-- for 13 (Base ID, RTR, IDE) or 14 (Base ID, RTR, IDE, EDL) or 32 bits +-- (Base ID, SRR, IDE, Ext ID, RTR) or 33 (Base ID, SRR, IDE, Ext ID, RTR, +-- r1) or 33 (Base ID, SRR, IDE, Ext ID, RTR, EDL) bits based on frame type. +-- Force bus Recessive (reserved bits are dominant) and wait until sample +-- point. Check that Node is transmitting error frame. Check that ERR_CAPT +-- signals Form Error in Control field. Reset the node, Wait until integration +-- is over and check that ERR_CAPT is at its reset value (this is to check +-- that next loops will truly set ERR_CAPT). Repeat with each frame type! +-------------------------------------------------------------------------------- +-- Revision History: +-- 03.02.2020 Created file +-------------------------------------------------------------------------------- + +context work.ctu_can_synth_context; +context work.ctu_can_test_context; + +use lib.pkg_feature_exec_dispath.all; + +package err_capt_ctrl_form_feature is + procedure err_capt_ctrl_form_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ); +end package; + + +package body err_capt_ctrl_form_feature is + procedure err_capt_ctrl_form_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ) is + variable rand_value : real; + variable alc : natural; + + -- Some unit lost the arbitration... + -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec + variable unit_rec : natural := 0; + + variable ID_1 : natural := 1; + variable ID_2 : natural := 2; + variable r_data : std_logic_vector(31 downto 0) := + (OTHERS => '0'); + -- Generated frames + variable frame_1 : SW_CAN_frame_type; + variable frame_2 : SW_CAN_frame_type; + variable frame_rx : SW_CAN_frame_type; + + -- Node status + variable stat_1 : SW_status; + variable stat_2 : SW_status; + + variable pc_dbg : SW_PC_Debug; + + variable txt_buf_state : SW_TXT_Buffer_state_type; + variable rx_buf_info : SW_RX_Buffer_info; + variable frames_equal : boolean := false; + + variable id_vect : std_logic_vector(28 downto 0); + variable wait_time : natural; + + variable err_counters_1_1 : SW_error_counters; + variable err_counters_1_2 : SW_error_counters; + + variable err_counters_2_1 : SW_error_counters; + variable err_counters_2_2 : SW_error_counters; + + variable frame_sent : boolean; + + variable err_capt : SW_error_capture; + + begin + + ----------------------------------------------------------------------- + -- 1. Check that ERR_CAPT contains no error (post reset). + ----------------------------------------------------------------------- + info("Step 1"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!"); + + ----------------------------------------------------------------------- + -- 2. Generate CAN frame (CAN 2.0 Base only, CAN FD Base only, CAN 2.0 + -- Extended, CAN FD extended), send it by Node 1. Wait until + -- Arbitration field and wait for 13 (Base ID, RTR, IDE) or 14 (Base + -- ID, RTR, IDE, EDL) or 34 bits (Base ID, SRR, IDE, Ext ID, RTR) or + -- 35 (Base ID, SRR, IDE, Ext ID, RTR, r1) or 35 (Base ID, SRR, IDE, + -- Ext ID, RTR, EDL) bits based on frame type. Force bus Recessive + -- (reserved bits are dominant) and wait until sample point. Check + -- that Node is transmitting error frame. Check that ERR_CAPT signals + -- Form Error in Control field. Reset the node, Wait until integration + -- is over and check that ERR_CAPT is at its reset value (this is to + --- check that next loops will truly set ERR_CAPT). Repeat with each + -- frame type! + ----------------------------------------------------------------------- + for i in 1 to 5 loop + info ("Inner Loop: " & integer'image(i)); + CAN_generate_frame(rand_ctr, frame_1); + + -- ID is not important in this TC. Avoid overflows of high generated + -- IDs on Base IDs! + frame_1.identifier := 10; + -- This is to avoid failing assertions on simultaneous RTR and EDL + -- flag (if r0 is corrupted by TC to be recessive!). RTR flag is + -- not important in this TC, therefore we can afford to fixate it! + frame_1.RTR := NO_RTR_FRAME; + + case i is + when 1 => + frame_1.frame_format := NORMAL_CAN; + frame_1.ident_type := BASE; + wait_time := 13; -- Till r0 + when 2 => + frame_1.frame_format := FD_CAN; + frame_1.ident_type := BASE; + wait_time := 14; -- Till r0 + when 3 => + frame_1.frame_format := NORMAL_CAN; + frame_1.ident_type := EXTENDED; + wait_time := 32; -- Till r1 + when 4 => + frame_1.frame_format := NORMAL_CAN; + frame_1.ident_type := EXTENDED; + wait_time := 33; -- Till r0 + when 5 => + frame_1.frame_format := FD_CAN; + frame_1.ident_type := EXTENDED; + wait_time := 33; -- Till r0 + end case; + + CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent); + CAN_wait_pc_state(pc_deb_arbitration, ID_1, mem_bus(1)); + + info("Waiting for: " & integer'image(wait_time) & " bits!"); + for j in 1 to wait_time loop + CAN_wait_sample_point(iout(1).stat_bus, true); + end loop; + + -- Force bus for one bit time + force_bus_level(RECESSIVE, so.bl_force, so.bl_inject); + CAN_wait_sample_point(iout(1).stat_bus, false); + wait for 20 ns; -- To be sure that opposite bit is sampled! + release_bus_level(so.bl_force); + + -- Check errors + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, + "Error frame is being transmitted!"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_type = can_err_form, "Form error detected!"); + check(err_capt.err_pos = err_pos_ctrl, + "Error detected in Control field!"); + wait for 100 ns; -- For debug only to see waves properly! + + -- Reset the node + exec_SW_reset(ID_1, mem_bus(1)); + CAN_turn_controller(true, ID_1, mem_bus(1)); + CAN_wait_bus_on(ID_1, mem_bus(1)); + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_pos = err_pos_other, "Reset value other"); + end loop; + + wait for 100 ns; + + end procedure; + +end package body; diff --git a/test/feature/err_capt_data_bit_feature_tb.vhd b/test/feature/err_capt_data_bit_feature_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..9538af41592d6e2f4f745706a01330122076974e --- /dev/null +++ b/test/feature/err_capt_data_bit_feature_tb.vhd @@ -0,0 +1,186 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- ERR_CAPT[ERR_POS] = ERC_POS_DATA feature test - bit error. +-- +-- Verifies: +-- 1. Detection of bit error in Data field. +-- 2. Value of ERR_CAPT when bit error is detected in Data field. +-- +-- Test sequence: +-- 1. Check that ERR_CAPT contains no error (post reset). +-- 2. Generate CAN frame, send it by Node 1. Wait until data field. Wait for +-- random duration of data field. Force bus to opposite value as transmitted +-- bit wait until sample point. Check that error frame is being transmitted. +-- Check that ERR_CAPT signals bit error in data field! +-------------------------------------------------------------------------------- +-- Revision History: +-- 03.02.2020 Created file +-------------------------------------------------------------------------------- + +context work.ctu_can_synth_context; +context work.ctu_can_test_context; + +use lib.pkg_feature_exec_dispath.all; + +package err_capt_data_bit_feature is + procedure err_capt_data_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ); +end package; + + +package body err_capt_data_bit_feature is + procedure err_capt_data_bit_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ) is + variable rand_value : real; + variable alc : natural; + + -- Some unit lost the arbitration... + -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec + variable unit_rec : natural := 0; + + variable ID_1 : natural := 1; + variable ID_2 : natural := 2; + variable r_data : std_logic_vector(31 downto 0) := + (OTHERS => '0'); + -- Generated frames + variable frame_1 : SW_CAN_frame_type; + variable frame_2 : SW_CAN_frame_type; + variable frame_rx : SW_CAN_frame_type; + + -- Node status + variable stat_1 : SW_status; + variable stat_2 : SW_status; + + variable pc_dbg : SW_PC_Debug; + + variable txt_buf_state : SW_TXT_Buffer_state_type; + variable rx_buf_info : SW_RX_Buffer_info; + variable frames_equal : boolean := false; + + variable id_vect : std_logic_vector(28 downto 0); + variable wait_time : natural; + + variable err_counters_1_1 : SW_error_counters; + variable err_counters_1_2 : SW_error_counters; + + variable err_counters_2_1 : SW_error_counters; + variable err_counters_2_2 : SW_error_counters; + + variable frame_sent : boolean; + + variable err_capt : SW_error_capture; + variable tmp : natural; + begin + + ----------------------------------------------------------------------- + -- 1. Check that ERR_CAPT contains no error (post reset). + ----------------------------------------------------------------------- + info("Step 1"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!"); + + ----------------------------------------------------------------------- + -- 2. Generate CAN frame, send it by Node 1. Wait until data field. + -- Wait for random duration of data field. Force bus to opposite + -- value as transmitted bit wait until sample point. Check that + -- error frame is being transmitted. Check that ERR_CAPT signals bit + -- error in data field! + ----------------------------------------------------------------------- + info("Step 2"); + + CAN_generate_frame(rand_ctr, frame_1); + frame_1.rtr := NO_RTR_FRAME; + + -- Don't sample by SSP! + frame_1.brs := BR_NO_SHIFT; + + if (frame_1.data_length = 0) then + frame_1.data_length := 1; + decode_length(frame_1.data_length, frame_1.dlc); + end if; + + CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent); + CAN_wait_tx_rx_start(true, false, ID_1, mem_bus(1)); + CAN_wait_pc_state(pc_deb_data, ID_1, mem_bus(1)); + + -- Wait for random number of bits + rand_int_v(rand_ctr, (frame_1.data_length * 8) - 1, tmp); + info("Waiting for: " & integer'image(tmp) & " bits!"); + for i in 0 to tmp loop + CAN_wait_sample_point(iout(1).stat_bus, true); + end loop; + + CAN_wait_sync_seg(iout(1).stat_bus); + wait for 20 ns; + + force_bus_level(not iout(1).can_tx, so.bl_force, so.bl_inject); + CAN_wait_sample_point(iout(1).stat_bus, false); + wait for 20 ns; -- To be sure that opposite bit is sampled! + release_bus_level(so.bl_force); + + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, "Error frame is being transmitted!"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_type = can_err_bit, "Bit error detected!"); + check(err_capt.err_pos = err_pos_data, "Error detected in Data field!"); + + CAN_wait_bus_idle(ID_1, mem_bus(1)); + + wait for 100 ns; + + end procedure; + +end package body; diff --git a/test/feature/err_capt_sof_feature_tb.vhd b/test/feature/err_capt_sof_feature_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..a71db934de6a85320d216440ad742b155b8720e2 --- /dev/null +++ b/test/feature/err_capt_sof_feature_tb.vhd @@ -0,0 +1,154 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- ERR_CAPT[ERR_POS] = ERC_POS_SOF feature test. +-- +-- Verifies: +-- 1. Detection of form error in SOF bit. +-- +-- Test sequence: +-- 1. Generate CAN frame and send it by Node 1. Wait until transmission starts +-- and force bus Recessive. Wait until sample point and check that Error +-- frame is transmitted. Check that ERR_CAPT says that Form Error during +-- SOF was detected! +-------------------------------------------------------------------------------- +-- Revision History: +-- 02.02.2020 Created file +-------------------------------------------------------------------------------- + +context work.ctu_can_synth_context; +context work.ctu_can_test_context; + +use lib.pkg_feature_exec_dispath.all; + +package err_capt_sof_feature is + procedure err_capt_sof_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ); +end package; + + +package body err_capt_sof_feature is + procedure err_capt_sof_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ) is + variable rand_value : real; + variable alc : natural; + + -- Some unit lost the arbitration... + -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec + variable unit_rec : natural := 0; + + variable ID_1 : natural := 1; + variable ID_2 : natural := 2; + variable r_data : std_logic_vector(31 downto 0) := + (OTHERS => '0'); + -- Generated frames + variable frame_1 : SW_CAN_frame_type; + variable frame_2 : SW_CAN_frame_type; + variable frame_rx : SW_CAN_frame_type; + + -- Node status + variable stat_1 : SW_status; + variable stat_2 : SW_status; + + variable pc_dbg : SW_PC_Debug; + + variable txt_buf_state : SW_TXT_Buffer_state_type; + variable rx_buf_info : SW_RX_Buffer_info; + variable frames_equal : boolean := false; + + variable id_vect : std_logic_vector(28 downto 0); + variable wait_time : natural; + + variable err_counters_1_1 : SW_error_counters; + variable err_counters_1_2 : SW_error_counters; + + variable err_counters_2_1 : SW_error_counters; + variable err_counters_2_2 : SW_error_counters; + + variable frame_sent : boolean; + + variable err_capt : SW_error_capture; + + begin + + ----------------------------------------------------------------------- + -- 1. Generate CAN frame and send it by Node 1. Wait until transmission + -- starts and force bus Recessive. Wait until sample point and check + -- that Error frame is transmitted. Check that ERR_CAPT says that + -- Form Error during SOF was detected! + ----------------------------------------------------------------------- + info("Step 1"); + + CAN_generate_frame(rand_ctr, frame_1); + CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent); + CAN_wait_tx_rx_start(true, false, ID_1, mem_bus(1)); + + force_bus_level(RECESSIVE, so.bl_force, so.bl_inject); + CAN_wait_sample_point(iout(1).stat_bus, false); + wait for 20 ns; -- To be sure that opposite bit is sampled! + release_bus_level(so.bl_force); + + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, "Error frame is being transmitted!"); + + CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1)); + check(err_capt.err_type = can_err_form, "Form error detected!"); + check(err_capt.err_pos = err_pos_sof, "Error detected in SOF!"); + + CAN_wait_bus_idle(ID_1, mem_bus(1)); + + wait for 100 ns; + + end procedure; + +end package body; diff --git a/test/feature/ssp_cfg_feature_tb.vhd b/test/feature/ssp_cfg_feature_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..1332192194af812e2fdb31fb367937a679ebe6c3 --- /dev/null +++ b/test/feature/ssp_cfg_feature_tb.vhd @@ -0,0 +1,378 @@ +-------------------------------------------------------------------------------- +-- +-- CTU CAN FD IP Core +-- Copyright (C) 2015-2018 +-- +-- Authors: +-- Ondrej Ille +-- Martin Jerabek +-- +-- Project advisors: +-- Jiri Novak +-- Pavel Pisa +-- +-- Department of Measurement (http://meas.fel.cvut.cz/) +-- Faculty of Electrical Engineering (http://www.fel.cvut.cz) +-- Czech Technical University (http://www.cvut.cz/) +-- +-- Permission is hereby granted, free of charge, to any person obtaining a copy +-- of this VHDL component and associated documentation files (the "Component"), +-- to deal in the Component without restriction, including without limitation +-- the rights to use, copy, modify, merge, publish, distribute, sublicense, +-- and/or sell copies of the Component, and to permit persons to whom the +-- Component is furnished to do so, subject to the following conditions: +-- +-- The above copyright notice and this permission notice shall be included in +-- all copies or substantial portions of the Component. +-- +-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS +-- IN THE COMPONENT. +-- +-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. +-- Anybody who wants to implement this IP core on silicon has to obtain a CAN +-- protocol license from Bosch. +-- +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- +-- Purpose: +-- SSP_CFG register feature test. +-- +-- Verifies: +-- 1. When SSP_CFG[SSP_SRC] = SSP_OFFSET, position of secondary sampling point +-- will be given only by SSP_OFFSET. +-- 2. When SSP_CFG[SSP_SRC] = SSP_SRC_NO_SSP, there will be no SSP and regular +-- sample point will be used to detect bit error by bit-error detector! +-- 3. When SSP_CFG[SSP_SRC] = SSP_SRC_MEAS_N_OFFSET, position of secondary +-- sampling point will be given as SSP_OFFSET + TRV_DELAY. +-- 4. Position of Secondary sampling point is saturated to 255. +-- 5. Transmitter detecting bit error in SSP will transmitt error frame at +-- nearest regular sample point, not earlier! +-- +-- Test sequence: +-- 1. Generate random TRV_DELAY between 0 and 125. Configure it in TB as delay +-- between CAN TX and CAN RX. +-- 2. Generate random SSP_CFG[SSP_SRC]. If it is offset only, generate +-- SSP_OFFSET which is higher than TRV_DELAY. If it is SSP_SRC_MEAS_N_OFFSET, +-- set SSP_OFFSET to random value between 0 and 255. Saturate calculated +-- value of SSP_SRC at 255. If it is SSP_SRC_NO_SSP, calculate SSP position +-- from regular data-bit rate. +-- 3. Generate random CAN FD frame with bit-rate shift. Wait until bit-rate is +-- shifted and wait for random number of bits (but do not exceed length of +-- data phase). Wait until edge on CAN TX or CAN RX. Store transmitted value +-- on CAN TX after the edge. Wait for expected position of Secondary sample +-- point - 3 clock cycles. +-- 4. Now we are 3 clock cycles before Secondary sampling point. Force bus to +-- opposite value than was sent. Check that Secondary sample point is active +-- (via Status Bus), if SSP_CFG[SSP_SRC] /= SSP_SRC_NO_SSP. Check that it is +-- not active when SSP_CFG[SSP_SRC] = SSP_SRC_NO_SSP. +-- 5. Wait for one clock cycle and if SSP_CFG[SSP_SRC] = SSP_SRC_NO_SSP, error +-- frame is being transmitted (regular sample point should be used to detect +-- bit errors). If SSP_CFG[SSP_SRC] /= SSP_SRC_NO_SSP check that Error frame +-- is not transmitted and wait until nearest Sample point. Check that after +-- this sample point, error frame is transmitted. Wait until bus is idle in +-- both nodes. +-------------------------------------------------------------------------------- +-- Revision History: +-- 02.1.2020 Created file +-------------------------------------------------------------------------------- + +context work.ctu_can_synth_context; +context work.ctu_can_test_context; + +use lib.pkg_feature_exec_dispath.all; + +package ssp_cfg_feature is + procedure ssp_cfg_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ); +end package; + + +package body ssp_cfg_feature is + procedure ssp_cfg_feature_exec( + signal so : out feature_signal_outputs_t; + signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; + signal iout : in instance_outputs_arr_t; + signal mem_bus : inout mem_bus_arr_t; + signal bus_level : in std_logic + ) is + variable rand_value : real; + variable alc : natural; + + -- Some unit lost the arbitration... + -- 0 - initial , 1-Node 1 turned rec, 2 - Node 2 turned rec + variable unit_rec : natural := 0; + + variable ID_1 : natural := 1; + variable ID_2 : natural := 2; + variable r_data : std_logic_vector(31 downto 0) := + (OTHERS => '0'); + -- Generated frames + variable frame_1 : SW_CAN_frame_type; + variable frame_2 : SW_CAN_frame_type; + variable frame_rx : SW_CAN_frame_type; + + -- Node status + variable stat_1 : SW_status; + variable stat_2 : SW_status; + + variable pc_dbg : SW_PC_Debug; + + variable txt_buf_state : SW_TXT_Buffer_state_type; + variable rx_buf_info : SW_RX_Buffer_info; + variable frames_equal : boolean := false; + variable frame_sent : boolean; + + variable id_vect : std_logic_vector(28 downto 0); + variable command : SW_command := SW_command_rst_val; + + variable num_frames : integer; + variable mode_1 : SW_mode; + + variable rand_trv_delay : natural; + variable tmp : natural; + + variable ssp_source : SSP_set_command_type; + variable ssp_offset_var : std_logic_vector(7 downto 0); + variable ssp_pos : natural; + + variable bus_timing : bit_time_config_type; + variable num_bit_waits : natural; + variable num_bit_waits_max : natural; + variable tx_val : std_logic; + + begin + + ----------------------------------------------------------------------- + -- 1. Generate random TRV_DELAY between 0 and 125. Configure it in TB + -- as delay between CAN TX and CAN RX. + ----------------------------------------------------------------------- + info("Step 1"); + + CAN_turn_controller(false, ID_1, mem_bus(1)); + CAN_turn_controller(false, ID_2, mem_bus(2)); + + -- Should be 250 Kbit/s + bus_timing.prop_nbt := 37; + bus_timing.ph1_nbt := 37; + bus_timing.ph2_nbt := 25; + bus_timing.tq_nbt := 4; + bus_timing.sjw_nbt := 5; + + -- Should be 2 Mbit/s + bus_timing.prop_dbt := 10; + bus_timing.ph1_dbt := 20; + bus_timing.ph2_dbt := 19; + bus_timing.tq_dbt := 1; + bus_timing.sjw_dbt := 5; + + -- We configure Nominal bit-rate to 500 Kbit/s so that generated + -- TRV_DELAY will not cause error frames in arbitration bit-rate! + CAN_configure_timing(bus_timing, ID_1, mem_bus(1)); + CAN_configure_timing(bus_timing, ID_2, mem_bus(2)); + + rand_int_v(rand_ctr, 1259, rand_trv_delay); + if (rand_trv_delay = 0) then + rand_trv_delay := 1; + end if; + + ----------------------------------------------------------------------- + -- Here we avoid explicit multiples of 10 ns! The reason is following: + -- When delay is e.g. 120 ns, then value will arrive at CAN RX when + -- rising_edge is active. Therefore sampled value might, or might not + -- be processed by clock based on which delta cycle was processed + -- first (Since signal delayer does not work with system clocks, it + -- might not be processed the same way as e.g. shift register!) + -- This would cause occasional test failures based on which process + -- was executed first (either rising_edge sampling the data, or data + -- delayed by signal delayer). + ----------------------------------------------------------------------- + if (rand_trv_delay mod 10 = 0) then + rand_trv_delay := rand_trv_delay + 1; + end if; + + ----------------------------------------------------------------------- + -- 2. Generate random SSP_CFG[SSP_SRC]. If it is offset only, generate + -- SSP_OFFSET which is higher than TRV_DELAY. If it is + -- SSP_SRC_MEAS_N_OFFSET, set SSP_OFFSET to random value between 0 + -- and 255. Saturate calculated value of SSP_SRC at 255. If it is + -- SSP_SRC_NO_SSP, calculate SSP position from regular data-bit rate. + ----------------------------------------------------------------------- + info("Step 2"); + + -- Init values + ssp_offset_var := (OTHERS => '0'); + ssp_source := ssp_meas_n_offset; + + info("SSP source:"); + rand_int_v(rand_ctr, 2, tmp); + if (tmp = 0) then + info("TRV_DELAY + Offset"); + ssp_source := ssp_meas_n_offset; + rand_logic_vect_v (rand_ctr, ssp_offset_var, 0.3); + + -- SSP position is offset + delay + info("SSP offset: " & integer'image(to_integer(unsigned(ssp_offset_var)))); + info("Trv delay div: " & integer'image(rand_trv_delay / 10)); + + ssp_pos := to_integer(unsigned(ssp_offset_var)) + rand_trv_delay / 10; + if (ssp_pos > 255) then + ssp_pos := 255; + end if; + + -- This is to compensate input delay of CTU CAN FD! See Datasheet. + -- section 2.5.3. This applies only for case without Datasheet + ssp_pos := ssp_pos + 2; + + elsif (tmp = 1) then + info("NO SSP"); + ssp_source := ssp_no_ssp; + + CAN_read_timing_v(bus_timing, ID_1, mem_bus(1)); + ssp_pos := bus_timing.tq_dbt * + (bus_timing.prop_dbt + bus_timing.ph1_dbt + 1); + + + -- In case of no SSP, we sample by regular sample point. Due to this, + -- we need to shorten trvdelay to less than delay of regular sample + -- point! SP in data sample here is in 20 + 10 + 1 = 31 System clocks. + -- Consider 2 clock cycle input delay and 1 cycle reserve! + rand_int_v(rand_ctr, 280, rand_trv_delay); + if (rand_trv_delay mod 10 = 0) then + rand_trv_delay := rand_trv_delay + 1; + end if; + else + info("Offset only"); + ssp_source := ssp_offset; + rand_logic_vect_v (rand_ctr, ssp_offset_var, 0.3); + + -- Here lengthen the SSP offset so that we are sufficiently over TRV_DELAY! + -- It should be enough to lengthen it by two clock cycles (input delay of + -- CTU CAN FD) + one cycle reserve for truncation of non-multiple of 10 + -- divided by 10! + if (to_integer(unsigned(ssp_offset_var)) <= rand_trv_delay/10) then + ssp_offset_var := std_logic_vector(to_unsigned(rand_trv_delay/10, 8) + 3); + end if; + + -- SSP position is offset only! + ssp_pos := to_integer(unsigned(ssp_offset_var)); + if (ssp_pos > 255) then + ssp_pos := 255; + end if; + end if; + + info("Random TRV_DELAY is: " & integer'image(rand_trv_delay) & " ns"); + ftr_tb_set_tran_delay((rand_trv_delay * 1 ns), ID_1, so.ftr_tb_trv_delay); + + info("SSP position: " & integer'image(ssp_pos)); + CAN_configure_ssp(ssp_source, ssp_offset_var, ID_1, mem_bus(1)); + CAN_configure_ssp(ssp_source, ssp_offset_var, ID_2, mem_bus(2)); + + CAN_turn_controller(true, ID_1, mem_bus(1)); + CAN_turn_controller(true, ID_2, mem_bus(2)); + + -- Wait till integration is over! + CAN_wait_bus_on(ID_1, mem_bus(1)); + CAN_wait_bus_on(ID_2, mem_bus(2)); + + ----------------------------------------------------------------------- + -- 3. Generate random CAN FD frame with bit-rate shift. Wait until + -- bit-rate is shifted and wait for random number of bits (but do + -- not exceed length of data phase). Wait until edge on CAN TX or + -- CAN RX. Store transmitted value on CAN TX after the edge. Wait + -- for expected position of Secondary sample point - 3 clock cycle. + ----------------------------------------------------------------------- + info("Step 3"); + + CAN_generate_frame(rand_ctr, frame_1); + frame_1.frame_format := FD_CAN; + frame_1.brs := BR_SHIFT; + + CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent); + CAN_wait_pc_state(pc_deb_control, ID_1, mem_bus(1)); + CAN_wait_not_pc_state(pc_deb_control, ID_1, mem_bus(1)); + + -- +10 is to cover some part of CRC + num_bit_waits_max := frame_1.data_length * 8 + 10 ; + rand_int_v(rand_ctr, num_bit_waits_max, num_bit_waits); + + info ("Frame data length: " & integer'image(frame_1.data_length * 8) & + " bits"); + info ("Waiting for: " & integer'image(num_bit_waits) & " bits"); + for i in 0 to num_bit_waits - 1 loop + CAN_wait_sample_point(iout(1).stat_bus, false); + end loop; + + -- Wait until edge is transmitted (for sure start of bit) and then + -- until expected sample point + wait until rising_edge(iout(1).can_tx) or falling_edge(iout(1).can_tx); + wait for 1 ps; + tx_val := iout(1).can_tx; + wait for (ssp_pos - 3) * 10 ns; + + ----------------------------------------------------------------------- + -- 4. Now we are 3 cycles before Secondary sampling point. Force bus + -- to opposite value than was sent. Check that Secondary sample point + -- is active (via Status Bus), if SSP_CFG[SSP_SRC] /= SSP_SRC_NO_SSP. + -- Check that it is not active when SSP_CFG[SSP_SRC] = SSP_SRC_NO_SSP. + ----------------------------------------------------------------------- + info("Step 4"); + force_bus_level(not tx_val, so.bl_force, so.bl_inject); + + -- Now we should be in the cycle where SSP is active!! + wait for 21 ns; + + if (ssp_source = ssp_no_ssp) then + check(iout(1).stat_bus(STAT_SAMPLE_SEC) = '0', + "SSP Sample point NOT active!"); + else + check(iout(1).stat_bus(STAT_SAMPLE_SEC) = '1', + "SSP Sample point active!"); + end if; + + ----------------------------------------------------------------------- + -- 5. Wait for one clock cycle and if SSP_CFG[SSP_SRC] = SSP_SRC_NO_SSP, + -- error frame is being transmitted (regular sample point should be + -- used to detect bit errors). If SSP_CFG[SSP_SRC] /= SSP_SRC_NO_SSP + -- check that Error frame is not transmitted and wait until nearest + -- Sample point. Check that after this Sample point, error frame is + -- transmitted. Wait until bus is idle in both nodes. + ----------------------------------------------------------------------- + info("Step 5"); + + wait for 11 ns; + + if (ssp_source = ssp_no_ssp) then + wait for 20 ns; + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, + "Error frame transmitted with NO_SSP"); + else + get_controller_status(stat_1, ID_1, mem_bus(1)); + check_false (stat_1.error_transmission, + "Error frame NOT transmitted yet!"); + CAN_wait_sample_point(iout(1).stat_bus, false); + wait for 21 ns; + get_controller_status(stat_1, ID_1, mem_bus(1)); + check (stat_1.error_transmission, + "Error frame transmitted after nearest sample point!"); + end if; + + release_bus_level(so.bl_force); + + CAN_wait_bus_idle(ID_1, mem_bus(1)); + CAN_wait_bus_idle(ID_2, mem_bus(2)); + + end procedure; + +end package body; diff --git a/test/feature/ssp_offset_feature_tb.vhd b/test/feature/ssp_offset_feature_tb.vhd deleted file mode 100644 index 43ced5b4cd168044d59cd465691abf2cf8a8a6ea..0000000000000000000000000000000000000000 --- a/test/feature/ssp_offset_feature_tb.vhd +++ /dev/null @@ -1,166 +0,0 @@ --------------------------------------------------------------------------------- --- --- CTU CAN FD IP Core --- Copyright (C) 2015-2018 --- --- Authors: --- Ondrej Ille --- Martin Jerabek --- --- Project advisors: --- Jiri Novak --- Pavel Pisa --- --- Department of Measurement (http://meas.fel.cvut.cz/) --- Faculty of Electrical Engineering (http://www.fel.cvut.cz) --- Czech Technical University (http://www.cvut.cz/) --- --- Permission is hereby granted, free of charge, to any person obtaining a copy --- of this VHDL component and associated documentation files (the "Component"), --- to deal in the Component without restriction, including without limitation --- the rights to use, copy, modify, merge, publish, distribute, sublicense, --- and/or sell copies of the Component, and to permit persons to whom the --- Component is furnished to do so, subject to the following conditions: --- --- The above copyright notice and this permission notice shall be included in --- all copies or substantial portions of the Component. --- --- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR --- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, --- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE --- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER --- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING --- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS --- IN THE COMPONENT. --- --- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. --- Anybody who wants to implement this IP core on silicon has to obtain a CAN --- protocol license from Bosch. --- --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- --- Purpose: --- Feature test for retransmitt limitation --- --------------------------------------------------------------------------------- --- Revision History: --- 30.6.2016 Created file --- 06.02.2018 Modified to work with the IP-XACT generated memory map --- 12.06.2018 Modified to use CAN Test lib instead of direct register --- access functions. --------------------------------------------------------------------------------- - -context work.ctu_can_synth_context; -context work.ctu_can_test_context; - -use lib.pkg_feature_exec_dispath.all; - -package ssp_offset_feature is - procedure ssp_offset_feature_exec( - signal so : out feature_signal_outputs_t; - signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; - signal iout : in instance_outputs_arr_t; - signal mem_bus : inout mem_bus_arr_t; - signal bus_level : in std_logic - ); -end package; - - -package body ssp_offset_feature is - procedure ssp_offset_feature_exec( - signal so : out feature_signal_outputs_t; - signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE; - signal iout : in instance_outputs_arr_t; - signal mem_bus : inout mem_bus_arr_t; - signal bus_level : in std_logic - ) is - variable data : std_logic_vector(31 downto 0) := - (OTHERS => '0'); - variable address : std_logic_vector(11 downto 0) := - (OTHERS => '0'); - - variable CAN_frame : SW_CAN_frame_type; - variable frame_sent : boolean := false; - variable ID_1 : natural := 1; - variable ID_2 : natural := 2; - variable retr_th : natural; - - variable mode : SW_mode := (false, false, false, - false, true, false, false, - false, false, false); - variable err_counters : SW_error_counters := (0, 0, 0, 0); - variable buf_state : SW_TXT_Buffer_state_type; - - variable ssp_source : SSP_set_command_type; - variable ssp_offset : std_logic_vector(6 downto 0); - begin - - ------------------------------------------------------------------------ - -- Set both nodes to forbid acknowledge - ------------------------------------------------------------------------ - -- mode.acknowledge_forbidden := true; - -- set_core_mode(mode, ID_1, mem_bus(1)); - -- set_core_mode(mode, ID_2, mem_bus(2)); - -- mode.acknowledge_forbidden := false; - - ------------------------------------------------------------------------ - -- Configure SSP_CFG on Node 1 - ------------------------------------------------------------------------ - ssp_source := ssp_measured; - ssp_offset := (OTHERS => '0'); - CAN_configure_ssp(ssp_source, ssp_offset, ID_1, mem_bus(1)); - - ------------------------------------------------------------------------ - -- Generate and send FD frame by Node 1 - ------------------------------------------------------------------------ - CAN_generate_frame(rand_ctr, CAN_frame); - CAN_frame.frame_format := NORMAL_CAN; --FD_CAN; - --CAN_frame.rtr := NO_RTR_FRAME; - -- CAN_frame.brs := BR_NO_SHIFT; --BR_SHIFT; - CAN_send_frame(CAN_frame, 1, ID_1, mem_bus(1), frame_sent); - - ------------------------------------------------------------------------ - -- Waits until reception is started by a Node 2. - ------------------------------------------------------------------------ - CAN_wait_tx_rx_start(false, true, ID_2, mem_bus(2)); - - -- počkat si na BRS bit - -- vynulovat si čítač a přičítat clockly hodiny - -- počkat až dostanu signal od SSP - -- přečíst čítat - -- vyhodnotit, jestli čítač načítal, co jsem nastavil - - - -- Wait till transmission is done - CAN_wait_frame_sent(ID_1, mem_bus(1)); - - CAN_wait_bus_idle(ID_2, mem_bus(2)); - CAN_wait_bus_idle(ID_1, mem_bus(1)); - ------------------------------------------------------------------------ - -- Wait number of retransmissions. After each one, TXT Buffer should - -- be back in ready. After last one, it should be in failed. - ------------------------------------------------------------------------ - --for i in 0 to retr_th loop - -- CAN_wait_frame_sent(ID_1, mem_bus(1)); - --get_tx_buf_state(1, buf_state, ID_1, mem_bus(1)); - -- if (i /= retr_th) then - -- check(buf_state = buf_ready, "TXT Buffer not ready"); - -- else - -- check(buf_state = buf_failed, "TXT Buffer not failed"); - -- end if; - -- end loop; - - ------------------------------------------------------------------------ - -- Read TX Counter, it should be equal to 8 times number of retransmitts - -- plus one original transmittion does not count as retransmittion. - ------------------------------------------------------------------------ - read_error_counters(err_counters, ID_1, mem_bus(1)); - check(err_counters.tx_counter = 8 * (retr_th + 1), - "Counters exp: " & Integer'Image(err_counters.tx_counter) & - " counters real: " & Integer'image(8 * (retr_th + 1))); - - - end procedure; - -end package body; \ No newline at end of file diff --git a/test/lib/CANtestLib.vhd b/test/lib/CANtestLib.vhd index 21b481b49656dd3403b9b85e09d7a0fe4ad1c6c7..190e7dfc5d3d091e0c01a69782a9358725578bfa 100644 --- a/test/lib/CANtestLib.vhd +++ b/test/lib/CANtestLib.vhd @@ -2069,16 +2069,23 @@ package CANtestLib is -- Wait until sample point (from Status Bus). -- -- Arguments: - -- pc_dbg State to poll on. - -- skip_stuff_bits When true, bits which are destuffed are skipped, only - -- bits counted by protocol control are taken into account. - -- When false, also stuff bits are taken into account. + -- stat_bus Status bus signal + -- skip_stuff_bits Whether stuff bits should be skipped or accounted. ---------------------------------------------------------------------------- procedure CAN_wait_sample_point( signal stat_bus : in std_logic_vector(511 downto 0); constant skip_stuff_bits : in boolean := true ); + ---------------------------------------------------------------------------- + -- Wait until start of bit (Sync Seg), (from Status Bus). + -- + -- Arguments: + -- pc_dbg State to poll on. + ---------------------------------------------------------------------------- + procedure CAN_wait_sync_seg( + signal stat_bus : in std_logic_vector(511 downto 0) + ); ---------------------------------------------------------------------------- -- Initialize TXT Buffer memories @@ -2971,6 +2978,7 @@ package body CANtestLib is signal ts_preset_val : out std_logic_vector(63 downto 0) )is begin + info ("Timestamp value to set: " & to_hstring(ts_value)); ts_preset_val <= ts_value; wait for 0 ns; @@ -5055,6 +5063,19 @@ package body CANtestLib is wait until stat_bus(STAT_RX_TRIGGER) = '1'; end if; end procedure; + + procedure CAN_wait_sync_seg( + signal stat_bus : in std_logic_vector(511 downto 0) + ) is + begin + while true loop + wait until stat_bus(STAT_TX_TRIGGER); + wait for 1 ps; + if (stat_bus(STAT_TX_TRIGGER) = '1') then + return; + end if; + end loop; + end procedure; procedure CAN_init_txtb_mems( diff --git a/test/tests_fast.yml b/test/tests_fast.yml index e485f3c2cc7c6a21e503bdc6524240c7a6f59d30..3489b39b155247cc91b7c2dd5659843469352ac0 100644 --- a/test/tests_fast.yml +++ b/test/tests_fast.yml @@ -60,6 +60,12 @@ feature: command_frcrst: device_id: dlc_can20_8_64_bytes: + err_capt_arb_bit: + err_capt_crc_bit: + err_capt_ctrl_bit: + err_capt_ctrl_form: + err_capt_data_bit: + err_capt_sof: err_norm_fd: error_rules_a: error_rules_b: @@ -96,6 +102,7 @@ feature: rx_buf_empty_read: tx_counter: rx_counter: + ssp_cfg: status_rxne: status_txnf: status_eft: diff --git a/test/tests_nightly.yml b/test/tests_nightly.yml index eb41d869e2cbb557aa7b7035003a8a08b4d7a7c3..7d8e413597d92cc3dc53854f0c04ae4b2beaeec6 100644 --- a/test/tests_nightly.yml +++ b/test/tests_nightly.yml @@ -91,6 +91,12 @@ feature: command_frcrst: device_id: dlc_can20_8_64_bytes: + err_capt_arb_bit: + err_capt_crc_bit: + err_capt_ctrl_bit: + err_capt_ctrl_form: + err_capt_data_bit: + err_capt_sof: err_norm_fd: iterations: 5 error_rules_a: @@ -129,6 +135,7 @@ feature: rx_buf_empty_read: tx_counter: rx_counter: + ssp_cfg: status_rxne: status_txnf: status_eft: diff --git a/test/wave_files/feature_err_capt_sof.gtkw b/test/wave_files/feature_err_capt_sof.gtkw new file mode 100644 index 0000000000000000000000000000000000000000..d2745c3c9850920b29f36a7575b0d58e2386710e --- /dev/null +++ b/test/wave_files/feature_err_capt_sof.gtkw @@ -0,0 +1,42 @@ +[*] +[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI +[*] Thu Jan 2 18:32:03 2020 +[*] +[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_feature.err_capt_sof_284efd78b8ceccd5c281a9a4579b7829b1e15644/ghdl/wave.ghw" +[dumpfile_mtime] "Thu Jan 2 18:29:52 2020" +[dumpfile_size] 2110746 +[savefile] "/build/test/wave_files/feature_err_capt_sof.gtkw" +[timestart] 19692000000 +[size] 1853 1025 +[pos] -1 -1 +*-29.000000 21290000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.tb_feature. +[treeopen] top.tb_feature.test_comp. +[treeopen] top.tb_feature.test_comp.g_inst[1]. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst. +[sst_width] 399 +[signals_width] 262 +[sst_expanded] 1 +[sst_vpaned_height] 300 +@28 +top.tb_feature.test_comp.g_inst[1].can_inst.can_tx +top.tb_feature.test_comp.g_inst[1].can_inst.can_rx +@420 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state +@28 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.err_frm_req +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.is_sof +@22 +#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[7:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[7] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[6] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[5] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[4] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[3] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.erc_capture[0] +@28 +#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[2:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_type_q[0] +@29 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_frm_req_i +@22 +#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[4:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[4] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[3] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[2] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_pos_q[0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/test/wave_files/feature_ssp_cfg.gtkw b/test/wave_files/feature_ssp_cfg.gtkw new file mode 100644 index 0000000000000000000000000000000000000000..0fee87e42ae0fa3928d1a418aabed2c78a53e7c4 --- /dev/null +++ b/test/wave_files/feature_ssp_cfg.gtkw @@ -0,0 +1,87 @@ +[*] +[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI +[*] Thu Jan 2 16:45:05 2020 +[*] +[dumpfile] "/build/test/build/vunit_out/test_output/lib.tb_feature.ssp_cfg_6b3f34bebbfdb95587c32c773c491935cbc75b9f/ghdl/wave.ghw" +[dumpfile_mtime] "Thu Jan 2 16:40:57 2020" +[dumpfile_size] 5368639 +[savefile] "/build/test/wave_files/feature_ssp_cfg.gtkw" +[timestart] 133913100000 +[size] 1853 1025 +[pos] -1 -1 +*-26.130369 133970000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.tb_feature. +[treeopen] top.tb_feature.test_comp. +[treeopen] top.tb_feature.test_comp.g_inst[1]. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst. +[treeopen] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst. +[sst_width] 410 +[signals_width] 360 +[sst_expanded] 1 +[sst_vpaned_height] 481 +@200 +-Node 1 +@28 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.clk_sys +top.tb_feature.test_comp.g_inst[1].can_inst.can_tx +top.tb_feature.test_comp.g_inst[1].can_inst.can_rx +@420 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.curr_state +top.tb_feature.test_comp.g_inst[1].can_inst.prescaler_inst.bit_time_fsm_inst.current_state +@28 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.protocol_control_fsm_inst.state_reg_ce +@420 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.operation_control_inst.curr_state +@28 +#{top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.sp_control[1:0]} top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.sp_control[1] top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.sp_control[0] +[color] 1 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.tx_trigger +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.rx_trigger +[color] 2 +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.sample_sec +@200 +-Bus injection +@28 +top.tb_feature.test_comp.bl_inject +@420 +top.tb_feature.test_comp.bl_force +@200 +-Bit error detection +@28 +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_condition +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.data_tx_delayed +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.data_rx_synced +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_capt_d +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.bit_err_ssp_capt_q +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.bit_err_d +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.bit_err_q +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err +top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.bit_err_detector_inst.rx_trigger +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.bit_err_enable +top.tb_feature.test_comp.g_inst[1].can_inst.can_core_inst.protocol_control_inst.err_detector_inst.err_frm_req_i +@200 +-Memory Bus +@22 +#{top.tb_feature.test_comp.g_inst[1].can_inst.adress[15:0]} top.tb_feature.test_comp.g_inst[1].can_inst.adress[15] top.tb_feature.test_comp.g_inst[1].can_inst.adress[14] top.tb_feature.test_comp.g_inst[1].can_inst.adress[13] top.tb_feature.test_comp.g_inst[1].can_inst.adress[12] top.tb_feature.test_comp.g_inst[1].can_inst.adress[11] top.tb_feature.test_comp.g_inst[1].can_inst.adress[10] top.tb_feature.test_comp.g_inst[1].can_inst.adress[9] top.tb_feature.test_comp.g_inst[1].can_inst.adress[8] top.tb_feature.test_comp.g_inst[1].can_inst.adress[7] top.tb_feature.test_comp.g_inst[1].can_inst.adress[6] top.tb_feature.test_comp.g_inst[1].can_inst.adress[5] top.tb_feature.test_comp.g_inst[1].can_inst.adress[4] top.tb_feature.test_comp.g_inst[1].can_inst.adress[3] top.tb_feature.test_comp.g_inst[1].can_inst.adress[2] top.tb_feature.test_comp.g_inst[1].can_inst.adress[1] top.tb_feature.test_comp.g_inst[1].can_inst.adress[0] +#{top.tb_feature.test_comp.g_inst[1].can_inst.data_out[31:0]} top.tb_feature.test_comp.g_inst[1].can_inst.data_out[31] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[30] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[29] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[28] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[27] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[26] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[25] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[24] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[23] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[22] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[21] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[20] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[19] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[18] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[17] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[16] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[15] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[14] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[13] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[12] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[11] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[10] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[9] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[8] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[7] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[6] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[5] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[4] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[3] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[2] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[1] top.tb_feature.test_comp.g_inst[1].can_inst.data_out[0] +#{top.tb_feature.test_comp.g_inst[1].can_inst.data_in[31:0]} top.tb_feature.test_comp.g_inst[1].can_inst.data_in[31] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[30] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[29] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[28] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[27] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[26] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[25] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[24] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[23] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[22] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[21] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[20] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[19] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[18] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[17] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[16] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[15] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[14] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[13] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[12] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[11] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[10] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[9] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[8] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[7] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[6] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[5] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[4] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[3] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[2] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[1] top.tb_feature.test_comp.g_inst[1].can_inst.data_in[0] +@28 +top.tb_feature.test_comp.g_inst[1].can_inst.scs +@200 +-Trv delay meas +@29 +#{top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.drv_ssp_delay_select[1:0]} top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.drv_ssp_delay_select[1] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.drv_ssp_delay_select[0] +@24 +#{top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[7:0]} top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[7] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[6] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[5] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[4] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[3] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[2] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[1] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_offset[0] +#{top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[7:0]} top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[7] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[6] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[5] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[4] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[3] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[2] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[1] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.trv_delay_measurement_inst.ssp_delay_shadowed[0] +#{top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[7:0]} top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[7] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[6] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[5] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[4] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[3] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[2] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[1] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.ssp_delay[0] +#{top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[14:0]} top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[14] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[13] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[12] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[11] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[10] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[9] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[8] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[7] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[6] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[5] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[4] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[3] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[2] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[1] top.tb_feature.test_comp.g_inst[1].can_inst.bus_sampling_inst.ssp_generator_inst.sspc_q[0] +[pattern_trace] 1 +[pattern_trace] 0