Commit 62134b7b authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Code formatting 2

parent fec36762
......@@ -5,7 +5,7 @@ use ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.ID_transfer.all;
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
......@@ -30,111 +30,174 @@ use work.ID_transfer.all;
-- Revision History:
--
-- July 2015 Created file
-- 17.1.2016 Added ID change from register value to decimal value for range filter comparison
-- 1.6.2016 Fixed wrong enable decoding from driving bus signals! Filters were disabled but
-- 17.1.2016 Added ID change from register value to decimal value for range
-- filter comparison
-- 1.6.2016 Fixed wrong enable decoding from driving bus signals! Filters
-- were disabled but
-- frame was anyway propagated to the output!
-------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Message filter for recieved data. Combinational circuit with valid data register at output of circuit.-
-- Filter identifier type, frame type are controlled by drv_bus from registers. 13 bit and 29 bit filters-
-- can be compared. If 13 bit filters are compared then MSB 16 bits in rec_ident_in has to be zeros. -
-- Also mask for the filter in case of 13-bit filter HAS to have 16 uppest bits equal to zero! It is set -
-- by drv_bus signals from control registers. Filters A,B,C,D are present. If input identifier matches -
-- at least one it is considered as valid. Frame type (CAN Basic, CAN Extended, CAN FD Basic) are also -
-- selectable for filtering. -
------------------------------------------------------------------------------------------------------------
-- Message filter for recieved data. Combinational circuit with valid data re-
-- gister at output of circuit. Filter identifier type, frame type are contro-
-- lled by drv_bus from registers. 13 bit and 29 bit filters can be compared.
-- If 13 bit filters are compared then MSB 16 bits in rec_ident_in has to be
-- zeros. Also mask for the filter in case of 13-bit filter HAS to have 16
-- uppest bits equal to zero! It is set by drv_bus signals from control regis-
-- ters. Filters A,B,C,D are present. If input identifier matches at least one
-- it is considered as valid. Frame type (CAN Basic, CAN Extended, CAN FD Basic)
-- are also selectable for filtering.
--------------------------------------------------------------------------------
entity messageFilter is
generic
(
constant sup_filtA :boolean := true; --Optional synthesis of received message filters
constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present
--Optional synthesis of received message filters
--By default the behaviour is as if all the filters are present
constant sup_filtA :boolean := true;
constant sup_filtB :boolean := true;
constant sup_filtC :boolean := true;
constant sup_range :boolean := true
);
port(
----------
--INPUTS--
----------
--Clock an reset signals
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async reset
----------------------------
-- Clock an reset signals
----------------------------
signal clk_sys :in std_logic; --System clock
signal res_n :in std_logic; --Async reset
--Driving signals from CAN Core
signal rec_ident_in :in std_logic_vector(28 downto 0); --Receieved identifier
signal ident_type :in std_logic; --Input message identifier type
-- (0-BASE Format, 1-Extended Format);
signal frame_type :in std_logic; --Input frame type (0-Normal CAN, 1- CAN FD)
signal rec_ident_valid :in std_logic; --Identifier valid (active log 1)
----------------------------------
-- Driving signals from CAN Core
----------------------------------
--Receieved identifier
signal rec_ident_in :in std_logic_vector(28 downto 0);
--Input message identifier type
-- (0-BASE Format, 1-Extended Format);
signal ident_type :in std_logic;
--Input frame type (0-Normal CAN, 1- CAN FD)
signal frame_type :in std_logic;
--Identifier valid (active log 1)
signal rec_ident_valid :in std_logic;
--Driving bus from registers
signal drv_bus :in std_logic_vector(1023 downto 0);
-----------
--OUTPUTS--
-----------
signal out_ident_valid :out std_logic --Signal whenever identifier matches the filter identifiers
------------------------------------------------------------
--Signal whenever identifier matches the filter identifiers
------------------------------------------------------------
signal out_ident_valid :out std_logic
);
---------------------------
--INTERNAL SIGNAL aliases -
---------------------------
signal drv_filter_A_mask :std_logic_vector(28 downto 0); --Filter A bit mask
signal drv_filter_A_ctrl :std_logic_vector(3 downto 0); --Filter A control bits
signal drv_filter_A_bits :std_logic_vector(28 downto 0); --Filter A bits
signal int_filter_A_valid :std_logic; --Output of filter A is valid (internal signal)
signal drv_filter_B_mask :std_logic_vector(28 downto 0); --Filter B bit mask
signal drv_filter_B_ctrl :std_logic_vector(3 downto 0); --Filter B control bits
signal drv_filter_B_bits :std_logic_vector(28 downto 0); --Filter B bits
signal int_filter_B_valid :std_logic; --Output of filter B is valid (internal signal)
signal drv_filter_C_mask :std_logic_vector(28 downto 0); --Filter C bit mask
signal drv_filter_C_ctrl :std_logic_vector(3 downto 0); --Filter C control bits
signal drv_filter_C_bits :std_logic_vector(28 downto 0); --Filter C bits
signal int_filter_C_valid :std_logic; --Output of filter C is valid (internal signal)
------------------------------------------------------------------------------
--INTERNAL SIGNAL aliases
------------------------------------------------------------------------------
--Filter A bit mask
signal drv_filter_A_mask :std_logic_vector(28 downto 0);
--Filter A control bits
signal drv_filter_A_ctrl :std_logic_vector(3 downto 0);
--Filter A bits
signal drv_filter_A_bits :std_logic_vector(28 downto 0);
--Output of filter A is valid (internal signal)
signal int_filter_A_valid :std_logic;
--Filter B bit mask
signal drv_filter_B_mask :std_logic_vector(28 downto 0);
--Filter B control bits
signal drv_filter_B_ctrl :std_logic_vector(3 downto 0);
--Filter B bits
signal drv_filter_B_bits :std_logic_vector(28 downto 0);
--Output of filter B is valid (internal signal)
signal int_filter_B_valid :std_logic;
--Filter C bit mask
signal drv_filter_C_mask :std_logic_vector(28 downto 0);
--Filter C control bits
signal drv_filter_C_ctrl :std_logic_vector(3 downto 0);
--Filter C control bits
signal drv_filter_C_bits :std_logic_vector(28 downto 0);
--Output of filter C is valid (internal signal)
signal int_filter_C_valid :std_logic;
signal drv_filter_ran_ctrl :std_logic_vector(3 downto 0); --Range filter control bits
signal drv_filter_ran_lo_th :std_logic_vector(28 downto 0); --Lower range filter trehsold
signal drv_filter_ran_hi_th :std_logic_vector(28 downto 0); --Upper range filter trehsold
signal int_filter_ran_valid :std_logic; --Output of range filter is valid
--Range filter control bits
signal drv_filter_ran_ctrl :std_logic_vector(3 downto 0);
--Lower range filter trehsold
signal drv_filter_ran_lo_th :std_logic_vector(28 downto 0);
--Upper range filter trehsold
signal drv_filter_ran_hi_th :std_logic_vector(28 downto 0);
--Output of range filter is valid
signal int_filter_ran_valid :std_logic;
--Enable the message filters
signal drv_filters_ena :std_logic;
--Internal aliases for input frame type
signal int_data_type :std_logic_vector(3 downto 0); --Frame type on input to be compared with driving signal
signal int_data_ctrl :std_logic_vector(1 downto 0); --Concat of types of data on input
--Frame type on input to be compared with driving signal
signal int_data_type :std_logic_vector(3 downto 0);
--Concat of types of data on input
signal int_data_ctrl :std_logic_vector(1 downto 0);
signal rec_ident_dec :natural; --Actual decimal value of recieved
--Actual decimal value of recieved
signal rec_ident_dec :natural;
--Decimal values of identifiers
signal id_1_dec :natural;
signal id_2_dec :natural;
-------------
--REGISTERS--
-------------
signal valid_reg:std_logic; --Register for valid output value
------------------------------------------------------------------------------
--REGISTERS
------------------------------------------------------------------------------
signal valid_reg:std_logic; --Register for valid output value
end entity;
architecture rtl of messageFilter is
begin
--Driving signal aliases
drv_filter_A_mask <= drv_bus(DRV_FILTER_A_MASK_HIGH downto DRV_FILTER_A_MASK_LOW);
drv_filter_A_ctrl <= drv_bus(DRV_FILTER_A_CTRL_HIGH downto DRV_FILTER_A_CTRL_LOW);
drv_filter_A_bits <= drv_bus(DRV_FILTER_A_BITS_HIGH downto DRV_FILTER_A_BITS_LOW);
drv_filter_B_mask <= drv_bus(DRV_FILTER_B_MASK_HIGH downto DRV_FILTER_B_MASK_LOW);
drv_filter_B_ctrl <= drv_bus(DRV_FILTER_B_CTRL_HIGH downto DRV_FILTER_B_CTRL_LOW);
drv_filter_B_bits <= drv_bus(DRV_FILTER_B_BITS_HIGH downto DRV_FILTER_B_BITS_LOW);
drv_filter_C_mask <= drv_bus(DRV_FILTER_C_MASK_HIGH downto DRV_FILTER_C_MASK_LOW);
drv_filter_C_ctrl <= drv_bus(DRV_FILTER_C_CTRL_HIGH downto DRV_FILTER_C_CTRL_LOW);
drv_filter_C_bits <= drv_bus(DRV_FILTER_C_BITS_HIGH downto DRV_FILTER_C_BITS_LOW);
drv_filter_ran_ctrl <= drv_bus(DRV_FILTER_RAN_CTRL_HIGH downto DRV_FILTER_RAN_CTRL_LOW);
drv_filter_ran_lo_th <= drv_bus(DRV_FILTER_RAN_LO_TH_HIGH downto DRV_FILTER_RAN_LO_TH_LOW);
drv_filter_ran_hi_th <= drv_bus(DRV_FILTER_RAN_HI_TH_HIGH downto DRV_FILTER_RAN_HI_TH_LOW);
drv_filter_A_mask <= drv_bus(DRV_FILTER_A_MASK_HIGH downto
DRV_FILTER_A_MASK_LOW);
drv_filter_A_ctrl <= drv_bus(DRV_FILTER_A_CTRL_HIGH downto
DRV_FILTER_A_CTRL_LOW);
drv_filter_A_bits <= drv_bus(DRV_FILTER_A_BITS_HIGH downto
DRV_FILTER_A_BITS_LOW);
drv_filter_B_mask <= drv_bus(DRV_FILTER_B_MASK_HIGH downto
DRV_FILTER_B_MASK_LOW);
drv_filter_B_ctrl <= drv_bus(DRV_FILTER_B_CTRL_HIGH downto
DRV_FILTER_B_CTRL_LOW);
drv_filter_B_bits <= drv_bus(DRV_FILTER_B_BITS_HIGH downto
DRV_FILTER_B_BITS_LOW);
drv_filter_C_mask <= drv_bus(DRV_FILTER_C_MASK_HIGH downto
DRV_FILTER_C_MASK_LOW);
drv_filter_C_ctrl <= drv_bus(DRV_FILTER_C_CTRL_HIGH downto
DRV_FILTER_C_CTRL_LOW);
drv_filter_C_bits <= drv_bus(DRV_FILTER_C_BITS_HIGH downto
DRV_FILTER_C_BITS_LOW);
drv_filter_ran_ctrl <= drv_bus(DRV_FILTER_RAN_CTRL_HIGH downto
DRV_FILTER_RAN_CTRL_LOW);
drv_filter_ran_lo_th <= drv_bus(DRV_FILTER_RAN_LO_TH_HIGH downto
DRV_FILTER_RAN_LO_TH_LOW);
drv_filter_ran_hi_th <= drv_bus(DRV_FILTER_RAN_HI_TH_HIGH downto
DRV_FILTER_RAN_HI_TH_LOW);
drv_filters_ena <= drv_bus(DRV_FILTERS_ENA_INDEX);
--Input frame type internal signal
......@@ -150,15 +213,17 @@ begin
--Filter A input frame type filtering
gen_filtA_pos: if (sup_filtA=true) generate
int_filter_A_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_A_mask) =
(drv_filter_A_bits AND drv_filter_A_mask)
int_filter_A_valid <= '1' when (( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_A_mask)
=
(drv_filter_A_bits AND drv_filter_A_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_A_ctrl AND int_data_type)="0000")
)
)
not((drv_filter_A_ctrl AND int_data_type)
= "0000")
)
)
else '0';
end generate;
......@@ -169,13 +234,15 @@ begin
--Filter B input frame type filtering
gen_filtB_pos: if (sup_filtB=true) generate
int_filter_B_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_B_mask) =
(drv_filter_B_bits AND drv_filter_B_mask)
)
int_filter_B_valid <= '1' when (( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_B_mask)
=
(drv_filter_B_bits AND drv_filter_B_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_B_ctrl AND int_data_type)="0000")
not((drv_filter_B_ctrl AND int_data_type)
= "0000")
)
)
else '0';
......@@ -188,13 +255,15 @@ begin
--Filter C input frame type filtering
gen_filtC_pos: if (sup_filtC=true) generate
int_filter_C_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_C_mask) =
(drv_filter_C_bits AND drv_filter_C_mask)
int_filter_C_valid <= '1' when (( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_C_mask)
=
(drv_filter_C_bits AND drv_filter_C_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_C_ctrl AND int_data_type)="0000")
not((drv_filter_C_ctrl AND int_data_type)
= "0000")
)
)
else '0';
......@@ -207,14 +276,19 @@ begin
--Range filter for identifiers
gen_filtRan_pos: if (sup_range=true) generate
ID_reg_to_decimal(rec_ident_in,rec_ident_dec);
int_filter_ran_valid <= '1' when ( --Identifier matches the range set
( rec_ident_dec<=to_integer(unsigned(drv_filter_ran_hi_th)) )
AND
( rec_ident_dec>=to_integer(unsigned(drv_filter_ran_lo_th)) )
int_filter_ran_valid <= '1' when (--Identifier matches the range set
(rec_ident_dec
<=
to_integer(unsigned(drv_filter_ran_hi_th)))
AND
(rec_ident_dec
>=
to_integer(unsigned(drv_filter_ran_lo_th)))
)
AND
( --Frame type Matches defined frame type
not((drv_filter_ran_ctrl AND int_data_type)="0000")
not((drv_filter_ran_ctrl AND int_data_type)
= "0000")
)
else '0';
end generate;
......@@ -227,21 +301,20 @@ begin
--If received message is valid and at least one of
-- the filters is matching the message passed the
-- filter.
valid_reg <= rec_ident_valid AND
valid_reg <= rec_ident_valid AND
(
int_filter_A_valid OR
int_filter_B_valid OR
int_filter_C_valid OR
int_filter_ran_valid
int_filter_A_valid OR
int_filter_B_valid OR
int_filter_C_valid OR
int_filter_ran_valid
) when drv_filters_ena='1'
else rec_ident_valid;
---------------------------------------------------
--To avoid long combinational paths, valid filter
-- output is pipelined. This is OK since received
-- frame is valid on input for many clock cycles!
---------------------------------------------------
------------------------------------------------------------------------------
--To avoid long combinational paths, valid filter output is pipelined. This is
--OK since received frame is valid on input for many clock cycles!
------------------------------------------------------------------------------
valid_reg_proc:process(res_n,clk_sys)
begin
if(res_n=ACT_RESET)then
......
This diff is collapsed.
......@@ -4,7 +4,7 @@ USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
......@@ -29,21 +29,25 @@ use work.CANconstants.all;
-- Revision History:
--
-- July 2015 Created file
-- 30.11.2017 Changed the buffer implementation from parallel into 32*20 buffer of data. Reading so far
-- left parallel. User is directly accessing the buffer and storing the data to it.
-- 04.12.2017 Buffer split to "Frame metadata" (txt_buffer_info) and "Data" (txt_buffer_data). Frame
-- metadata consists of first 4 words (Frame format, Timestamps and Identifier). Frame metadata
-- are available combinationally at all times. Frame data are accessed directly from CAN Core
-- by new pointer "txt_data_addr". txt_buffer_data is synthesized as RAM memory and significant
-- 30.11.2017 Changed the buffer implementation from parallel into 32*20
-- buffer of data. Reading so far left parallel. User is directly
-- accessing the buffer and storing the data to it.
-- 04.12.2017 Buffer split to "Frame metadata" (txt_buffer_info) and "Data"
-- (txt_buffer_data). Frame metadata consists of first 4 words
-- (Frame format, Timestamps and Identifier). Frame metadata are
-- available combinationally at all times. Frame data are accessed
-- directly from CAN Core by new pointer "txt_data_addr".
-- txt_buffer_data is synthesized as RAM memory and significant
-- reource reduction was achieved.
-------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Transmit message buffer. Access to TX_DATA_REG of user registers is combinationally mapped
-- to the TXT Buffers. User is storing the data directly into the TX buffer. Once the user allows to
-- transmitt from the buffer, content of the buffer is validated and "empty" is cleared.
---------------------------------------------------------------------------------------------------------
-- Transmit message buffer. Access to TX_DATA_REG of user registers is combi-
-- nationally mapped to the TXT Buffers. User is storing the data directly into
-- the TX buffer. Once the user allows to transmitt from the buffer, content of
-- the buffer is validated and "empty" is cleared.
--------------------------------------------------------------------------------
entity txtBuffer is
generic(
......@@ -55,34 +59,44 @@ entity txtBuffer is
--Clock and reset-
------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic; --Async reset
signal res_n :in std_logic; --Async reset
-------------------------------
--Driving Registers Interface--
-------------------------------
signal drv_bus :in std_logic_vector(1023 downto 0); --Driving bus
signal tran_data :in std_logic_vector(31 downto 0); --Data into the RAM of TXT Buffer
signal tran_addr :in std_logic_vector(4 downto 0); --Address in the RAM of TXT buffer
--Driving bus
signal drv_bus :in std_logic_vector(1023 downto 0);
--Data into the RAM of TXT Buffer
signal tran_data :in std_logic_vector(31 downto 0);
--Address in the RAM of TXT buffer
signal tran_addr :in std_logic_vector(4 downto 0);
------------------
--Status signals--
------------------
signal txt_empty :out std_logic; --Logic 1 signals empty TxTime buffer
--Logic 1 signals empty TxTime buffer
signal txt_empty :out std_logic;
------------------------------------
--CAN Core and TX Arbiter Interface-
------------------------------------
--Signal from TX Arbiter that data were transmitted and buffer can be erased
--Signal from TX Arbiter that data were transmitted and buffer
--can be erased
signal txt_data_ack :in std_logic;
-- Frame to be transmitted
-- Data of the frame to be transmitted and pointer to the RAM memory
-- of TXT buffer
signal txt_data_word :out std_logic_vector(31 downto 0);
signal txt_data_addr :in natural range 0 to 15;
--First 4 words (frame format, timestamps, identifier) are available combinationally,
--to be able instantly decide on higher priority frame
signal txt_frame_info_out :out std_logic_vector(127 downto 0)
--First 4 words (frame format, timestamps, identifier) are available
--combinationally, to be able instantly decide on higher priority frame
signal txt_frame_info_out :out std_logic_vector(127 downto 0)
);
......@@ -94,22 +108,31 @@ architecture rtl of txtBuffer is
----------------------
--Internal registers--
----------------------
type frame_data_memory is array(0 to 15) of
std_logic_vector(31 downto 0);
type frame_info_memory is array (0 to 3) of
std_logic_vector(31 downto 0);
type frame_data_memory is array(0 to 15) of std_logic_vector(31 downto 0);
type frame_info_memory is array (0 to 3) of std_logic_vector(31 downto 0);
------------------
--Signal aliases--
------------------
signal txt_buffer_data : frame_data_memory; -- Time transcieve buffer - Data memory
signal txt_buffer_info : frame_info_memory; -- Frame format, Timestamps and Identifier
-- Time transcieve buffer - Data memory
signal txt_buffer_data : frame_data_memory;
-- Frame format, Timestamps and Identifier
signal txt_buffer_info : frame_info_memory;
signal tran_wr : std_logic_vector(1 downto 0); -- Store into TXT buffer 1 or 2
signal txt_empty_reg : std_logic; -- Status of the register
-- Store into TXT buffer 1 or 2
signal tran_wr : std_logic_vector(1 downto 0);
-- Status of the register
signal txt_empty_reg : std_logic;
-- Allow/forbid transmission from the buffer
signal drv_allow : std_logic;
signal drv_allow : std_logic;
signal drv_allow_reg : std_logic; -- Registered value for the detection 0-1 transition and signalling that the buffer is full
-- Registered value for the detection 0-1 transition and signalling
-- that the buffer is full
signal drv_allow_reg : std_logic;
begin
......@@ -126,11 +149,14 @@ begin
txt_data_word <= txt_buffer_data(txt_data_addr);
--First 4 words of the Frame are available constantly...
txt_frame_info_out <= txt_buffer_info(0)&txt_buffer_info(1)&txt_buffer_info(2)&txt_buffer_info(3);
txt_frame_info_out <= txt_buffer_info(0)&
txt_buffer_info(1)&
txt_buffer_info(2)&
txt_buffer_info(3);
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Main buffer comment
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
tx_buf_proc:process(res_n,clk_sys)
begin
if (res_n = ACT_RESET) then
......@@ -151,7 +177,8 @@ begin
--Updating the value of empty either from Registers or TX Arbitrator
if (txt_data_ack='1') then
txt_empty_reg <= '1';
elsif (drv_allow_reg='0' and drv_allow='1') then -- 0-1 on drv_allow signals validation of the buffer content!
elsif (drv_allow_reg='0' and drv_allow='1') then
-- 0-1 on drv_allow signals validation of the buffer content!
txt_empty_reg <= '0';
else
txt_empty_reg <= txt_empty_reg;
......@@ -162,7 +189,7 @@ begin
if (tran_addr<4) then
txt_buffer_info(to_integer(unsigned(tran_addr))) <= tran_data;
else
txt_buffer_data(to_integer(unsigned(tran_addr-4))) <= tran_data;
txt_buffer_data(to_integer(unsigned(tran_addr-4))) <= tran_data;
end if;
end if;
......
......@@ -5,7 +5,7 @@ USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
-------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
......@@ -30,27 +30,35 @@ USE WORK.CANconstants.ALL;
-- Revision History:
--
-- July 2015 Created file
-- 19.12.2015 Added tripple sampling mode. Furthermore sampling is disabled when
-- whole controller is disabled
-- 15.6.2016 1.edge_tx_valid signal now provides edge detection only from RECESSIVE to DOMINANT
-- values! In CAN FD standard EDL and r0 bits are used for TRD measurment! When busSync is
-- configured to start on TX edge and finish on RX edge.
-- 2.Changed trv_delay size to cover mostly 127 clock cycles! Changed shift register sizes
-- to 130 to avoid missing secondary sample signals!!
-- 3.Fixed tripple sampling mode selection from three. Added missing signals
-- 4. trv_to_restart signal added to make it impossible to restart trv delay measurment
-- without rising edge on trv_delay calib signal. This removes a bug when trv_delay_calib
-- is forgottern active and circuit keeps measuring on every edge...
-- 27.6.2016 Bug fix added. Transciever delaye measurment conditions switched. Now starting edge is the
-- most prioritized logic. Thus transciever delay counter is always erased with TX edge!
-- 'elsif(edge_tx_valid='1')' swapped with 'if(trv_running='1')'. Thisway if more TX edge would
-- come before first RX edge is sampled, shorter time would be measured! Note that this is
-- OK since in CAN spec. EDL bit is in nominal bit time and no other edge can be transmitted
-- before it is recieved (condition of original CAN)
-- 19.12.2015 Added tripple sampling mode. Furthermore sampling is disabled
-- when whole controller is disabled
-- 15.6.2016 1.edge_tx_valid signal now provides edge detection only from
-- RECESSIVE to DOMINANT values! In CAN FD standard EDL and r0
-- bits are used for TRD measurment! When busSync is configured
-- to start on TX edge and finish on RX edge.
-- 2.Changed trv_delay size to cover mostly 127 clock cycles!
-- Changed shift register sizes to 130 to avoid missing secon-
-- dary sample signals!!
-- 3.Fixed tripple sampling mode selection from three. Added
-- missing signals
-- 4. trv_to_restart signal added to make it impossible to res-
-- tart trv delay measurment without rising edge on trv_delay
-- calib signal. This removes a bug when trv_delay_calib
-- is forgottern active and circuit keeps measuring on every
-- edge...
-- 27.6.2016 Bug fix. Transciever delay measurment conditions switched. Now
-- starting edge is the most prioritized logic. Thus transciever
-- delay counter is always erased with TX edge!
-- 'elsif(edge_tx_valid='1')' swapped with 'if(trv_running='1')'.
-- Thisway if more TX edge would come before first RX edge is
-- sampled, shorter time would be measured! Note that this is OK
-- since in CAN spec. EDL bit is in nominal bit time and no other
-- edge can be transmitted before it is recieved (condition of