Commit 60cd8fc5 authored by Pavel Pisa's avatar Pavel Pisa

synthesis/Quartus: Update Quartus CAN_Wrapper to match core after 194-protocol-control-rework.

Closes #297Signed-off-by: Pavel Pisa's avatarPavel Pisa <pisa@cmp.felk.cvut.cz>
parent 091e6489
Pipeline #9604 failed with stages
in 11 minutes and 21 seconds
......@@ -87,63 +87,86 @@ set_global_assignment -name VHDL_FILE CAN_Wrapper.vhd
# -------------------------------------------------------------------------- #
### CTU CAN FD core sources list - begin ###
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/memory_bus.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/address_decoder.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/data_mux.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/access_signaler.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/cmn_reg_map_pkg.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/event_logger_reg_map.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/can_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/control_registers_reg_map.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/memory_reg.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/memory_registers.vhd
set_global_assignment -name VHDL_FILE ../../src/apb/apb_ifc.vhd
set_global_assignment -name VHDL_FILE ../../src/bus_sampling/bit_err_detector.vhd
set_global_assignment -name VHDL_FILE ../../src/bus_sampling/bus_sampling.vhd
set_global_assignment -name VHDL_FILE ../../src/bus_sampling/data_edge_detector.vhd
set_global_assignment -name VHDL_FILE ../../src/bus_sampling/sample_mux.vhd
set_global_assignment -name VHDL_FILE ../../src/bus_sampling/trv_delay_meas.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/bit_destuffing/bit_destuffing.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/bit_stuffing/bit_stuffing.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/bus_traffic_counters/bus_traffic_counters.vhd
set_global_assignment -name VHDL_FILE ../../src/bus_sampling/tx_data_cache.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/bit_destuffing.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/bit_stuffing.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/bus_traffic_counters.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/can_core.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/crc/can_crc.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/crc/crc_calc.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/crc/crc_wrapper.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/fault_confinement/fault_confinement.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/operation_control/operation_control.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/protocol_control/protocol_control.vhd
set_global_assignment -name VHDL_FILE ../../src/can_top_apb.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/can_crc.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/control_counter.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/crc_calc.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/err_counters.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/err_detector.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/fault_confinement.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/fault_confinement_fsm.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/fault_confinement_rules.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/operation_control.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/protocol_control.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/protocol_control_fsm.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/reintegration_counter.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/retransmitt_counter.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/rx_shift_reg.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/trigger_mux.vhd
set_global_assignment -name VHDL_FILE ../../src/can_core/tx_shift_reg.vhd
set_global_assignment -name VHDL_FILE ../../src/common/dff_arst.vhd
set_global_assignment -name VHDL_FILE ../../src/common/endian_swap.vhd
set_global_assignment -name VHDL_FILE ../../src/common/dlc_decoder.vhd
set_global_assignment -name VHDL_FILE ../../src/common/endian_swapper.vhd
set_global_assignment -name VHDL_FILE ../../src/common/inf_ram_wrapper.vhd
set_global_assignment -name VHDL_FILE ../../src/common/majority_decoder_3.vhd
set_global_assignment -name VHDL_FILE ../../src/common/rst_sync.vhd
set_global_assignment -name VHDL_FILE ../../src/common/shift_reg.vhd
set_global_assignment -name VHDL_FILE ../../src/common/shift_reg_byte.vhd
set_global_assignment -name VHDL_FILE ../../src/common/shift_reg_preload.vhd
set_global_assignment -name VHDL_FILE ../../src/common/sig_sync.vhd
set_global_assignment -name VHDL_FILE ../../src/event_logger/event_logger.vhd
set_global_assignment -name VHDL_FILE ../../src/frame_filters/bit_filter.vhd
set_global_assignment -name VHDL_FILE ../../src/frame_filters/frame_filters.vhd
set_global_assignment -name VHDL_FILE ../../src/frame_filters/range_filter.vhd
set_global_assignment -name VHDL_FILE ../../src/interrupts/int_module.vhd
set_global_assignment -name VHDL_FILE ../../src/interrupts/int_manager.vhd
set_global_assignment -name VHDL_FILE ../../src/interrupts/int_module.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_components.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_config.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_constants.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_fd_frame_format.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_fd_register_map.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_types.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/cmn_lib.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/drv_stat_pkg.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/id_transfer.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/reduce_lib.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_components.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/can_fd_register_map.vhd
set_global_assignment -name VHDL_FILE ../../src/lib/drv_stat_pkg.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/access_signaler.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/address_decoder.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/data_mux.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/can_registers_pkg.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/cmn_reg_map_pkg.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/control_registers_reg_map.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/memory_bus.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/generated/memory_reg.vhd
set_global_assignment -name VHDL_FILE ../../src/memory_registers/memory_registers.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/bit_time_cfg_capture.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/bit_time_counters.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/bit_time_fsm.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/prescaler.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/resynchronisation.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/segment_end_detector.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/synchronisation_checker.vhd
set_global_assignment -name VHDL_FILE ../../src/prescaler/trigger_generator.vhd
set_global_assignment -name VHDL_FILE ../../src/rx_buffer/rx_buffer.vhd
set_global_assignment -name VHDL_FILE ../../src/rx_buffer/rx_buffer_fsm.vhd
set_global_assignment -name VHDL_FILE ../../src/rx_buffer/rx_buffer_pointers.vhd
set_global_assignment -name VHDL_FILE ../../src/rx_buffer/rx_buffer_ram.vhd
set_global_assignment -name VHDL_FILE ../../src/tx_arbitrator/priority_decoder.vhd
set_global_assignment -name VHDL_FILE ../../src/tx_arbitrator/tx_arbitrator.vhd
set_global_assignment -name VHDL_FILE ../../src/tx_arbitrator/tx_arbitrator_fsm.vhd
set_global_assignment -name VHDL_FILE ../../src/txt_buffer/txt_buffer.vhd
set_global_assignment -name VHDL_FILE ../../src/txt_buffer/txt_buffer_fsm.vhd
set_global_assignment -name VHDL_FILE ../../src/txt_buffer/txt_buffer_ram.vhd
set_global_assignment -name VHDL_FILE ../../src/can_top_apb.vhd
set_global_assignment -name VHDL_FILE ../../src/can_top_level.vhd
### CTU CAN FD core sources list - end ###
# -------------------------------------------------------------------------- #
......
......@@ -51,15 +51,12 @@ use work.can_components.ALL;
entity CAN_Wrapper is
generic (
constant use_logger : boolean := false;
constant rx_buffer_size : natural := 32;
constant use_sync : boolean:= true;
constant ID : natural:= 1;
constant sup_filtA : boolean:= true;
constant sup_filtB : boolean:= true;
constant sup_filtC : boolean:= true;
constant sup_range : boolean:= true;
constant logger_size : natural:= 8
constant ID : natural:= 1;
constant sup_filtA : boolean:= true;
constant sup_filtB : boolean:= true;
constant sup_filtC : boolean:= true;
constant sup_range : boolean:= true
);
port (
signal clk_sys : in std_logic;
......@@ -67,7 +64,7 @@ entity CAN_Wrapper is
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic; --Chip select
signal srd : in std_logic; --Serial read
signal swr : in std_logic; --Serial write
......@@ -200,15 +197,12 @@ begin
CAN_comp:CAN_top_level
generic map(
use_logger => use_logger,
rx_buffer_size => rx_buffer_size,
use_sync => use_sync,
ID => ID,
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
sup_filtC => sup_filtC,
sup_range => sup_range,
logger_size => logger_size
sup_range => sup_range
)
port map(
clk_sys => clk_sys,
......@@ -223,7 +217,6 @@ begin
int => int,
CAN_tx => CAN_tx,
CAN_rx => CAN_rx,
time_quanta_clk => time_quanta_clk,
timestamp => timestamp
);
......
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