Commit 5d5c1af9 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

update: reg_map regenerated.

parent 3d591e4d
......@@ -262,7 +262,7 @@ Control registers memory region.\end_layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="5" rows="39" version="3">
<lyxtabular columns="5" rows="40" version="3">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="3cm">
<column alignment="center" valignment="top" width="3cm">
......@@ -2511,6 +2511,48 @@ hyperref[YOLO_REG]{YOLO\backslash textunderscore REG}\end_layout
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
...\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
\begin_inset ERT
status open
......@@ -2568,7 +2610,7 @@ hyperref[TIMESTAMP_LOW]{TIMESTAMP\backslash textunderscore LOW}\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
0x8C\end_layout
0x90\end_layout
 
\end_inset
</cell>
......@@ -2634,7 +2676,7 @@ hyperref[TIMESTAMP_HIGH]{TIMESTAMP\backslash textunderscore HIGH}\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
0x90\end_layout
0x94\end_layout
 
\end_inset
</cell>
......@@ -33804,7 +33846,7 @@ label{TIMESTAMP_LOW
Type: read-only
\end_layout
\begin_layout Description
Address: 0x8C
Address: 0x90
\end_layout
\begin_layout Description
Size: 4 bytes
......@@ -34805,7 +34847,7 @@ label{TIMESTAMP_HIGH
Type: read-only
\end_layout
\begin_layout Description
Address: 0x90
Address: 0x94
\end_layout
\begin_layout Description
Size: 4 bytes
......
......@@ -87,8 +87,8 @@ enum ctu_can_fd_can_registers {
CTU_CAN_FD_TX_COUNTER = 0x80,
CTU_CAN_FD_DEBUG_REGISTER = 0x84,
CTU_CAN_FD_YOLO_REG = 0x88,
CTU_CAN_FD_TIMESTAMP_LOW = 0x8c,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x90,
CTU_CAN_FD_TIMESTAMP_LOW = 0x90,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x94,
CTU_CAN_FD_TXTB1_DATA_1 = 0x100,
CTU_CAN_FD_TXTB1_DATA_2 = 0x104,
CTU_CAN_FD_TXTB1_DATA_20 = 0x14c,
......
......@@ -103,8 +103,8 @@ package can_fd_register_map is
constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"080";
constant DEBUG_REGISTER_ADR : std_logic_vector(11 downto 0) := x"084";
constant YOLO_REG_ADR : std_logic_vector(11 downto 0) := x"088";
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"08C";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"090";
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"090";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"094";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......
......@@ -82,8 +82,8 @@ end entity control_registers_reg_map;
architecture rtl of control_registers_reg_map is
signal reg_sel : std_logic_vector(36 downto 0);
constant ADDR_VECT
: std_logic_vector(221 downto 0) := "100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(1183 downto 0);
: std_logic_vector(221 downto 0) := "100101100100100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(1215 downto 0);
signal read_data_mask_n : std_logic_vector(31 downto 0);
signal control_registers_out_i : Control_registers_out_t;
signal read_mux_ena : std_logic;
......@@ -779,7 +779,7 @@ begin
data_mux_control_registers_comp : data_mux
generic map(
data_out_width => 32 ,
data_in_width => 1184 ,
data_in_width => 1216 ,
sel_width => 6 ,
registered_out => REGISTERED_READ ,
reset_polarity => RESET_POLARITY
......@@ -798,12 +798,15 @@ begin
-- Read data driver
------------------------------------------------------------------------------
read_data_mux_in <=
-- Adress:144
-- Adress:148
control_registers_in.timestamp_high &
-- Adress:140
-- Adress:144
control_registers_in.timestamp_low &
-- Adress:140
"00000000" & "00000000" & "00000000" & "00000000" &
-- Adress:136
control_registers_in.yolo_reg &
......
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