Commit 5a547b6e authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

doc: Update generated Lyx Interfaces.

parent 6b97012c
......@@ -96,7 +96,7 @@ customHeadersFooters
\end_header
\begin_body
\begin_layout Subsection
\begin_layout Description
Generics\end_layout
\begin_layout Standard
\noindent
......@@ -210,13 +210,13 @@ Reset polarity\end_layout
\end_layout
\begin_layout Subsection
\begin_layout Description
Ports\end_layout
\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="17" version="3">
<lyxtabular columns="4" rows="16" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -678,40 +678,6 @@ Bit Destuffing is enabled.\end_layout
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
stuff_error_enable\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
in std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Stuff error detection enabled.\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
fixed_stuff\end_layout
......@@ -847,7 +813,7 @@ cellcolor{gray}
\begin_inset Text
\begin_layout Plain Layout
stuff_error\end_layout
stuff_err\end_layout
\end_inset
</cell>
......@@ -931,7 +897,11 @@ dst_ctr\end_layout
\begin_inset Text
\begin_layout Plain Layout
out natural range 0 to 7\end_layout
out std_logic_vector
\begin_inset Newline newline
\end_inset
(2 downto 0)\end_layout
\end_inset
</cell>
......
......@@ -96,7 +96,7 @@ customHeadersFooters
\end_header
\begin_body
\begin_layout Subsection
\begin_layout Description
Generics\end_layout
\begin_layout Standard
\noindent
......@@ -210,7 +210,7 @@ Reset polarity\end_layout
\end_layout
\begin_layout Subsection
\begin_layout Description
Ports\end_layout
\begin_layout Standard
\noindent
......@@ -829,7 +829,11 @@ out\end_layout
\begin_inset Text
\begin_layout Plain Layout
natural range 0 to 7\end_layout
std_logic_vector
\begin_inset Newline newline
\end_inset
(2 downto 0)\end_layout
\end_inset
</cell>
......
......@@ -96,7 +96,7 @@ customHeadersFooters
\end_header
\begin_body
\begin_layout Subsection
\begin_layout Description
Generics\end_layout
\begin_layout Standard
\noindent
......@@ -346,13 +346,13 @@ Optional usage of saturated value of ssp_delay\end_layout
\end_layout
\begin_layout Subsection
\begin_layout Description
Ports\end_layout
\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="21" version="3">
<lyxtabular columns="4" rows="22" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -685,7 +685,7 @@ CAN serial stream input\end_layout
\begin_inset Text
\begin_layout Plain Layout
Memorz registers interface\begin_inset ERT
Memory registers interface\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
......@@ -700,7 +700,7 @@ cellcolor{gray}
\begin_inset Text
\begin_layout Plain Layout
Memorz registers interface\begin_inset ERT
Memory registers interface\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
......@@ -715,7 +715,7 @@ cellcolor{gray}
\begin_inset Text
\begin_layout Plain Layout
Memorz registers interface\begin_inset ERT
Memory registers interface\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
......@@ -730,7 +730,7 @@ cellcolor{gray}
\begin_inset Text
\begin_layout Plain Layout
Memorz registers interface\begin_inset ERT
Memory registers interface\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
......@@ -805,7 +805,7 @@ std_logic_vector
\begin_inset Newline newline
\end_inset
(15 downto 0)\end_layout
(G_TRV_CTR_WIDTH - 1 downto 0)\end_layout
\end_inset
</cell>
......@@ -909,7 +909,41 @@ std_logic\end_layout
\begin_inset Text
\begin_layout Plain Layout
RX Trigger for Nominal Bit Time\end_layout
RX Trigger\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
tx_trigger\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
in\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
TX Trigger\end_layout
\end_inset
</cell>
......@@ -1223,7 +1257,7 @@ Secondary sampling RX trigger\end_layout
\begin_inset Text
\begin_layout Plain Layout
bit_error\end_layout
bit_err\end_layout
\end_inset
</cell>
......
......@@ -96,7 +96,7 @@ customHeadersFooters
\end_header
\begin_body
\begin_layout Subsection
\begin_layout Description
Generics\end_layout
\begin_layout Standard
\noindent
......@@ -448,13 +448,13 @@ CRC 15 polynomial\end_layout
\end_layout
\begin_layout Subsection
\begin_layout Description
Ports\end_layout
\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="55" version="3">
<lyxtabular columns="4" rows="58" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -1953,7 +1953,7 @@ Error is detected (Error frame will be transmitted)\end_layout
\begin_inset Text
\begin_layout Plain Layout
error_passive_changed\end_layout
fcs_changed\end_layout
\end_inset
</cell>
......@@ -1977,7 +1977,7 @@ std_logic\end_layout
\begin_inset Text
\begin_layout Plain Layout
Error passive state changed\end_layout
Fault confinement state changed\end_layout
\end_inset
</cell>
......@@ -1987,7 +1987,7 @@ Error passive state changed\end_layout
\begin_inset Text
\begin_layout Plain Layout
error_warning_limit\end_layout
err_warning_limit\end_layout
\end_inset
</cell>
......@@ -2013,6 +2013,40 @@ std_logic\end_layout
\begin_layout Plain Layout
Error warning limit reached\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
is_overload\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
out\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Overload frame is being transmitted\end_layout
\end_inset
</cell>
</row>
......@@ -2219,6 +2253,112 @@ std_logic\end_layout
\begin_layout Plain Layout
No positive resynchronisation\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
sp_control\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
out\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic_vector
\begin_inset Newline newline
\end_inset
(1 downto 0)\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Sample control (Nominal, Data, Secondary)\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
nbt_ctrs_en\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
out\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Enable Nominal Bit time counters.\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
dbt_ctrs_en\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
out\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Enable Data Bit time counters.\end_layout
\end_inset
</cell>
</row>
......@@ -2456,44 +2596,6 @@ std_logic_vector
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
sp_control\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
out\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic_vector
\begin_inset Newline newline
\end_inset
(1 downto 0)\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Sample control (Nominal, Data, Secondary)\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
ssp_reset\end_layout
......@@ -2563,7 +2665,7 @@ Enable measurement of Transciever delay\end_layout
\begin_inset Text
\begin_layout Plain Layout
bit_error\end_layout
bit_err\end_layout
\end_inset
</cell>
......
......@@ -96,7 +96,7 @@ customHeadersFooters
\end_header
\begin_body
\begin_layout Subsection
\begin_layout Description
Generics\end_layout
\begin_layout Standard
\noindent
......@@ -312,13 +312,13 @@ CRC 15 polynomial\end_layout
\end_layout
\begin_layout Subsection
\begin_layout Description
Ports\end_layout
\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="24" version="3">
<lyxtabular columns="4" rows="26" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -1146,6 +1146,40 @@ CRC calculation - speculative enable\end_layout
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
crc_calc_from_rx\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
in\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Use RX Data for CRC calculation\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
is_receiver\end_layout
......@@ -1173,6 +1207,40 @@ std_logic\end_layout
\begin_layout Plain Layout
Unit is receiver of a frame\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
load_init_vect\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
in\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Load CRC Initialization vector\end_layout
\end_inset
</cell>
</row>
......
......@@ -96,7 +96,7 @@ customHeadersFooters
\end_header
\begin_body
\begin_layout Subsection
\begin_layout Description
Generics\end_layout
\begin_layout Standard
\noindent
......@@ -380,13 +380,13 @@ Insert Range Filter\end_layout
\end_layout
\begin_layout Subsection
\begin_layout Description
Ports\end_layout
\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="4" rows="24" version="3">
<lyxtabular columns="4" rows="22" version="3">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -1130,102 +1130,6 @@ RX signal from CAN bus\end_layout
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Synchronisation signals\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
cellcolor{gray}
\end_layout
\end_inset
\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Synchronisation signals\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
cellcolor{gray}
\end_layout
\end_inset
\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Synchronisation signals\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
cellcolor{gray}
\end_layout
\end_inset
\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Synchronisation signals\begin_inset ERT