Fix of Reg. map generator. Added enable pin on address

decoder.

pyXact_generator @ 249c32ef

-Subproject commit 368f339184c019b5487887baf0f99c87b58557d8
+Subproject commit 249c32efd7a2b6c88fcf41d84450617faf1b5572

src/Registers_Memory_Interface/generated/address_decoder.vhd

@@ -30,6 +30,8 @@
 --------------------------------------------------------------------------------
 -- Revision History:
 --    14.10.2018   Created file
+--    07.12.2018   Added enable signal. Active only when enable is in logic 1,
+--                 otherwise disabled.
 --------------------------------------------------------------------------------
 
 Library ieee;
@@ -67,6 +69,11 @@ entity address_decoder is
         ------------------------------------------------------------------------
         signal address                :in   std_logic_vector(address_width - 1 downto 0);
 
+        ------------------------------------------------------------------------
+        -- Enable input
+        ------------------------------------------------------------------------
+        signal enable                 :in   std_logic;
+
         ------------------------------------------------------------------------
         -- Output, one-hot coded. In logic 1 for each valid address
         ------------------------------------------------------------------------
@@ -82,6 +89,10 @@ architecture rtl of address_decoder is
     signal addr_dec_i                 :   std_logic_vector(
                                                 address_entries - 1 downto 0);
     
+    -- Address after masking by enable input
+    signal addr_dec_enabled_i          :   std_logic_vector(
+                                                address_entries - 1 downto 0);
+
 begin
 
     ---------------------------------------------------------------------------
@@ -97,6 +108,13 @@ begin
     end generate addr_dec_gen;
 
 
+    ---------------------------------------------------------------------------
+    -- Address decoder enabled / disabled - masking
+    ---------------------------------------------------------------------------
+    addr_dec_enabled_i <= addr_dec_i when (enable = '1') else
+                          (OTHERS => '0');
+
+
     ---------------------------------------------------------------------------
     -- Registering / Not-registering output
     ---------------------------------------------------------------------------
@@ -107,14 +125,14 @@ begin
                 addr_dec <= (OTHERS => '0');
 
             elsif (rising_edge(clk_sys)) then
-                addr_dec <= addr_dec_i;
+                addr_dec <= addr_dec_enabled_i;
 
             end if;
         end process;
     end generate addr_dec_reg_true_gen;
 
     addr_dec_reg_false_gen : if (not registered_out) generate
-        addr_dec <= addr_dec_i;
+        addr_dec <= addr_dec_enabled_i;
     end generate addr_dec_reg_false_gen;
 
 

src/Registers_Memory_Interface/generated/cmn_reg_map_pkg.vhd

@@ -59,6 +59,7 @@ component address_decoder is
         signal clk_sys                :in   std_logic;
         signal res_n                  :in   std_logic;
         signal address                :in   std_logic_vector(address_width - 1 downto 0);
+        signal enable                 :in   std_logic;
         signal addr_dec               :out  std_logic_vector(address_entries - 1 downto 0)
     );
 end component address_decoder;

src/Registers_Memory_Interface/generated/control_registers_reg_map.vhd

@@ -105,6 +105,7 @@ begin
         clk_sys                         => clk_sys ,-- in
         res_n                           => res_n ,-- in
         address                         => address(7 downto 2) ,-- in
+        enable                          => cs ,-- in
         addr_dec                        => reg_sel -- out
     );
 
@@ -742,7 +743,7 @@ begin
     -- Read data multiplexor enable 
     ----------------------------------------------------------------------------
     read_data_keep_gen : if (CLEAR_READ_DATA = false) generate
-        read_mux_ena <= read;
+        read_mux_ena <= read and cs;
     end generate read_data_keep_gen;
 
     read_data_clear_gen : if (CLEAR_READ_DATA = true) generate

src/Registers_Memory_Interface/generated/event_logger_reg_map.vhd

@@ -101,6 +101,7 @@ begin
         clk_sys                         => clk_sys ,-- in
         res_n                           => res_n ,-- in
         address                         => address(7 downto 2) ,-- in
+        enable                          => cs ,-- in
         addr_dec                        => reg_sel -- out
     );
 
@@ -174,7 +175,7 @@ begin
     -- Read data multiplexor enable 
     ----------------------------------------------------------------------------
     read_data_keep_gen : if (CLEAR_READ_DATA = false) generate
-        read_mux_ena <= read;
+        read_mux_ena <= read and cs;
     end generate read_data_keep_gen;
 
     read_data_clear_gen : if (CLEAR_READ_DATA = true) generate