Commit 58aea321 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Add option to force timestamp in testbench.

parent 9e2de118
......@@ -58,6 +58,8 @@ package pkg_feature_exec_dispath is
bl_inject : std_logic;
bl_force : boolean;
ftr_tb_trv_delay : t_ftr_tx_delay;
ts_preset : std_logic_vector(2 downto 1);
ts_preset_val : std_logic_vector(63 downto 0);
end record;
constant NINST : natural := 2;
......
......@@ -88,6 +88,10 @@ entity CAN_feature_test is
-- Transmitter delays
signal transmitter_delays :in t_ftr_tx_delay;
-- Timestamp forcing (preset)
signal ts_preset : in std_logic_vector(2 downto 1);
signal ts_preset_val : in std_logic_vector(63 downto 0);
-- Internal signals; TODO: direction
signal iteration_done : in boolean := false;
......@@ -216,7 +220,8 @@ begin
---------------------------------
clk_gen_proc: clock_gen_proc(period => f100_Mhz, duty => 50,
epsilon_ppm => (i - 1) * 100, out_clk => p(i).clk_sys);
tsgen_proc: timestamp_gen_proc(p(i).clk_sys, p(i).timestamp);
tsgen_proc: timestamp_gen_proc(p(i).clk_sys, p(i).timestamp, ts_preset(i),
ts_preset_val);
end generate;
tr_proc:process(all)
......@@ -381,7 +386,9 @@ architecture tb of tb_feature is
((
11 * f100_Mhz * 1 ps,
11 * f100_Mhz * 1 ps
))
)),
"00",
(OTHERS => '0')
);
begin
......@@ -403,6 +410,9 @@ begin
bl_inject => bl_inject,
bl_force => bl_force,
transmitter_delays => ftr_tb_trv_delays,
ts_preset => so.ts_preset,
ts_preset_val => so.ts_preset_val,
iteration_done => iteration_done,
hw_reset_on_new_test => hw_reset_on_new_test,
......
......@@ -73,6 +73,8 @@
-- 15.9.2018 Added support for message filter manipulation!
-- 27.9.2018 Added burst support for avalon access. Added option to read
-- frame from RX Buffer via burst partially!
-- 19.11.2019 Added options to force transmitter delay and timestamp in
-- feature tests.
--------------------------------------------------------------------------------
Library ieee;
......@@ -698,7 +700,9 @@ package CANtestLib is
----------------------------------------------------------------------------
procedure timestamp_gen_proc(
signal clk : in std_logic;
signal timestamp : out std_logic_vector(63 downto 0)
signal timestamp : out std_logic_vector(63 downto 0);
signal ts_preset : in std_logic;
signal ts_preset_val : in std_logic_vector(63 downto 0)
);
......@@ -1095,6 +1099,7 @@ package CANtestLib is
-- Arguments:
-- tx_del Delay to be set
-- ID ID of the node where delay shall be set.
-- actual_delay Delay signal to force
----------------------------------------------------------------------------
procedure ftr_tb_set_tran_delay(
constant tx_del : in time;
......@@ -1102,6 +1107,23 @@ package CANtestLib is
signal actual_delay : out t_ftr_tx_delay
);
----------------------------------------------------------------------------
-- Configure timestamp in feature TB.
--
-- Arguments:
-- ts_value Value to be forced to timestamp.
-- ID ID of the node where delay shall be set.
-- ts_preset Vector controlling presetting.
-- ts_preset_val Value controlling presetting.
----------------------------------------------------------------------------
procedure ftr_tb_set_timestamp(
constant ts_value : in std_logic_vector(63 downto 0);
constant ID : in natural range 0 to 15;
signal ts_preset : out std_logic_vector;
signal ts_preset_val : out std_logic_vector(63 downto 0)
);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
......@@ -2195,7 +2217,9 @@ package body CANtestLib is
procedure timestamp_gen_proc(
signal clk : in std_logic;
signal timestamp : out std_logic_vector(63 downto 0)
signal timestamp : out std_logic_vector(63 downto 0);
signal ts_preset : in std_logic;
signal ts_preset_val : in std_logic_vector(63 downto 0)
) is
variable ts_lo : natural := 0;
variable tmp : natural := 0;
......@@ -2212,6 +2236,12 @@ package body CANtestLib is
ts_lo := tmp;
timestamp <= std_logic_vector( to_unsigned(ts_hi, 32)
& to_unsigned(ts_lo, 32));
if (ts_preset = '1') then
ts_lo := to_integer(unsigned(ts_preset_val(31 downto 0)));
ts_hi := to_integer(unsigned(ts_preset_val(63 downto 32)));
wait for 0 ns;
end if;
end loop;
end procedure;
......@@ -2918,6 +2948,33 @@ package body CANtestLib is
end procedure;
procedure ftr_tb_set_timestamp(
constant ts_value : in std_logic_vector(63 downto 0);
constant ID : in natural range 0 to 15;
signal ts_preset : out std_logic_vector;
signal ts_preset_val : out std_logic_vector(63 downto 0)
)is
begin
ts_preset_val <= ts_value;
wait for 0 ns;
if (ID = 1) then
ts_preset <= "01";
elsif (ID = 2) then
ts_preset <= "10";
end if;
-- This is ugly hack to achieve that timestamp generation process
-- will loop at least once and thus catch our action (system clock
-- is 10 ns).
wait for 11 ns;
ts_preset <= "00";
wait for 0 ns;
end procedure;
procedure CAN_configure_timing(
constant bus_timing : in bit_time_config_type;
constant ID : in natural range 0 to 15;
......
......@@ -97,6 +97,9 @@ architecture CAN_reference_test of CAN_test is
signal bit_sequence : bit_seq_type := ((OTHERS => 1), (OTHERS => '0'), 1);
constant ITER_PRESET : natural := 0;
signal ts_preset : std_logic_vector(2 downto 1) := "00";
signal ts_preset_val : std_logic_vector(63 downto 0) := (OTHERS => '0');
----------------------------------------------------------------------------
-- Config file with generated bit sequences
......@@ -312,7 +315,7 @@ begin
----------------------------------------------------------------------------
clk_gen_proc : clock_gen_proc(period => f100_Mhz, duty => 50,
epsilon_ppm => 0, out_clk => clk_sys);
tsgen_proc : timestamp_gen_proc(clk_sys, timestamp);
tsgen_proc : timestamp_gen_proc(clk_sys, timestamp, ts_preset(1), ts_preset_val);
----------------------------------------------------------------------------
-- Bit generator
......
......@@ -285,6 +285,9 @@ architecture behavioral of sanity_test is
-- Frame counter for all frames on the bus
signal overal_frame_counter : natural;
signal ts_preset : std_logic_vector(2 downto 1) := "00";
signal ts_preset_val : std_logic_vector(63 downto 0) := (OTHERS => '0');
----------------------------------------------
----------------------------------------------
......@@ -493,7 +496,7 @@ begin
----------------------------------------------------------------------------
clock_generic : for i in 1 to NODE_COUNT generate
clock_gen_proc(f100_mhz, 50, epsilon_v(i), mem_aux_clk(i));
timestamp_gen_proc(mem_aux_clk(i), timestamp_v(i));
timestamp_gen_proc(mem_aux_clk(i), timestamp_v(i), ts_preset(1), ts_preset_val);
end generate clock_generic;
......
......@@ -153,6 +153,9 @@ architecture rx_buf_unit_test of CAN_test is
signal mod_pointer : natural := 0;
constant C_RX_BUFF_SIZE : natural := 32;
signal ts_preset : std_logic_vector(2 downto 1) := "00";
signal ts_preset_val : std_logic_vector(63 downto 0) := (OTHERS => '0');
----------------------------------------------------------------------------
......@@ -546,7 +549,7 @@ begin
----------------------------------------------------------------------------
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
timestamp_gen_proc(clk_sys, timestamp);
timestamp_gen_proc(clk_sys, timestamp, ts_preset(1), ts_preset_val);
-- Overall amount of errors is sum of errors from all processes
error_ctr <= stim_errs + read_errs + status_errs + cons_errs;
......
......@@ -143,6 +143,9 @@ architecture tx_arb_unit_test of CAN_test is
signal sel_buf_mism : boolean;
signal mism_ctr : natural := 0;
signal ts_preset : std_logic_vector(2 downto 1) := "00";
signal ts_preset_val : std_logic_vector(63 downto 0) := (OTHERS => '0');
----------------------------------------------------------------------------
-- Compare function for two 64 bit std logic vectors
----------------------------------------------------------------------------
......@@ -578,7 +581,7 @@ begin
----------------------------------------------------------------------------
clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => clk_sys);
timestamp_gen_proc(clk_sys, timestamp);
timestamp_gen_proc(clk_sys, timestamp, ts_preset(1), ts_preset_val);
errors <= error_ctr;
......
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