Commit 5808ea4b authored by Martin Jeřábek's avatar Martin Jeřábek

tests: sanity: fix tcl layout

parent 2141c8c0
......@@ -44,7 +44,7 @@ global SILENT_SANITY
start_CAN_simulation "sanity_test_wrapper"
quietly set INST1 "can_inst_1"
quietly set CORE "core_top_comp"
quietly set CORE "can_core_comp"
################################################################################
# Adding the waves
......@@ -110,10 +110,10 @@ add wave -label "CAN Tx" -expand $WRCOMP/can_tx_v
add wave -label "CAN Rx" -expand $WRCOMP/can_rx_v
add wave -group "Protocol states" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/PC_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/PC_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/PC_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/PC_State
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/PC_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/PC_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/PC_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/PC_State
if { $SILENT_SANITY == "false" } {
add wave -group "Bit time state" \
......@@ -123,16 +123,16 @@ add wave -group "Bit time state" \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/bt_FSM_out
add wave -group "Trancieve triggers" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_trig
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_trig
add wave -group "Recieve triggers" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/rec_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/rec_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/rec_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/rec_trig
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/rec_trig \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/rec_trig \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/rec_trig \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/rec_trig
add wave -group "Hard sync edge" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/hard_sync_edge_valid \
......@@ -141,16 +141,16 @@ add wave -group "Hard sync edge" \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/hard_sync_edge_valid
add wave -group "Synchronization type" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/sync_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/sync_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/sync_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/sync_control
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/sync_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/sync_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/sync_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/sync_control
add wave -group "Sample control" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/sp_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/sp_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/sp_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/sp_control
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/sp_control \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/sp_control \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/sp_control \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/sp_control
add wave -group "Time quantum start" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/prescaler_comp/tq_edge \
......@@ -166,45 +166,45 @@ add wave -group "System clocks" \
}
add wave -group "Error states" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/error_state \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/error_state \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/error_state \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/error_state
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/error_state \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/error_state \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/error_state \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/error_state
add wave -group "Operation states" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/OP_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/OP_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/OP_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/OP_State
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/OP_State \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/OP_State \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/OP_State \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/OP_State
add wave -group "Identifier shift registers (Base part)" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/PC_State_comp/tran_ident_base_sr \
add wave -group "Identifiers shift registers (Extended part)" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/PC_State_comp/tran_ident_ext_sr \
add wave -group "RTR flag" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_is_rtr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_is_rtr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_is_rtr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_is_rtr
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_is_rtr \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_is_rtr \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_is_rtr \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_is_rtr
add wave -group "Identifier type" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_ident_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_ident_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_ident_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_ident_type
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_ident_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_ident_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_ident_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_ident_type
add wave -group "Frame type" \
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/core_top_comp/tran_frame_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/core_top_comp/tran_frame_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/core_top_comp/tran_frame_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/core_top_comp/tran_frame_type
-label "Node 1" $WRCOMP/comp_gen__1/node_1_comp/can_core_comp/tran_frame_type \
-label "Node 2" $WRCOMP/comp_gen__2/node_1_comp/can_core_comp/tran_frame_type \
-label "Node 3" $WRCOMP/comp_gen__3/node_1_comp/can_core_comp/tran_frame_type \
-label "Node 4" $WRCOMP/comp_gen__4/node_1_comp/can_core_comp/tran_frame_type
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