Commit 53e41a29 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src,test: Second batch of Vivado synthesis warnings.

parent 6e22a934
......@@ -519,7 +519,6 @@ begin
-- Operation control FSM Interface
is_transmitter => is_transmitter, -- IN
is_receiver => is_receiver, -- IN
is_idle => is_idle, -- IN
arbitration_lost => arbitration_lost_i, -- OUT
set_transmitter => set_transmitter, -- OUT
set_receiver => set_receiver, -- OUT
......@@ -702,7 +701,6 @@ begin
crc_enable => crc_enable, -- IN
crc_spec_enable => crc_spec_enable, -- IN
crc_calc_from_rx => crc_calc_from_rx, -- IN
is_receiver => is_receiver, -- IN
load_init_vect => load_init_vect, -- IN
-- CRC Outputs
......
......@@ -146,9 +146,6 @@ entity can_crc is
-- Use RX Data for CRC calculation
crc_calc_from_rx :in std_logic;
-- Unit is receiver of a frame
is_receiver :in std_logic;
-- Load CRC Initialization vector
load_init_vect :in std_logic;
......
......@@ -231,9 +231,6 @@ entity protocol_control is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......@@ -635,15 +632,13 @@ begin
---------------------------------------------------------------------------
endian_swapper_tx_inst : endian_swapper
generic map(
G_SWAP_BY_SIGNAL => false,
G_SWAP_GEN => true,
G_WORD_SIZE => 4, -- Number of Groups
G_GROUP_SIZE => 8 -- Group size (bits)
)
port map(
input => tran_word, -- IN
output => tran_word_swapped, -- OUT
swap_in => '0' -- IN
output => tran_word_swapped -- OUT
);
......@@ -780,7 +775,6 @@ begin
-- Operation control interface
is_transmitter => is_transmitter, -- IN
is_receiver => is_receiver, -- IN
is_idle => is_idle, -- IN
arbitration_lost => arbitration_lost_i, -- OUT
set_transmitter => set_transmitter, -- OUT
set_receiver => set_receiver, -- OUT
......
......@@ -427,9 +427,6 @@ entity protocol_control_fsm is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......
......@@ -68,11 +68,7 @@ use work.CAN_FD_frame_format.all;
entity endian_swapper is
generic (
-- If true, "swap_in" signal selects between swapping/non-swapping.
-- If false "swap_gen" generic selects bewtween swapping/non-swapping.
G_SWAP_BY_SIGNAL : boolean := false;
-- When true, output word is endian swapped as long as "swap_by_signal"
-- is true. Otherwise it has no meaning.
G_SWAP_GEN : boolean := false;
......@@ -88,11 +84,7 @@ entity endian_swapper is
input : in std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Data output
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Swap signal (used only when "swap_by_signal=true")
-- Swaps endian when '1', keeps otherwise.
swap_in : in std_logic
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0)
);
end entity;
......@@ -123,30 +115,19 @@ begin
input(u_ind_orig downto l_ind_orig);
end loop;
end process;
---------------------------------------------------------------------------
-- Swapping by generic
---------------------------------------------------------------------------
swap_by_generic_gen : if (not G_SWAP_BY_SIGNAL) generate
-- Swap
swap_by_generic_true_gen : if (G_SWAP_GEN) generate
output <= swapped;
end generate swap_by_generic_true_gen;
-- Don't Swap
swap_by_generic_false_gen : if (not G_SWAP_GEN) generate
output <= input;
end generate swap_by_generic_false_gen;
end generate swap_by_generic_gen;
-- Swap
swap_by_generic_true_gen : if (G_SWAP_GEN) generate
output <= swapped;
end generate swap_by_generic_true_gen;
---------------------------------------------------------------------------
-- Swapping by input
---------------------------------------------------------------------------
swap_by_input_gen : if (G_SWAP_BY_SIGNAL) generate
output <= swapped when (swap_in = '1') else
input;
end generate swap_by_input_gen;
-- Don't Swap
swap_by_generic_false_gen : if (not G_SWAP_GEN) generate
output <= input;
end generate swap_by_generic_false_gen;
end architecture;
......@@ -792,9 +792,6 @@ package can_components is
-- Use RX Data for CRC calculation
crc_calc_from_rx :in std_logic;
-- Unit is receiver of a frame
is_receiver :in std_logic;
-- Load CRC Initialization vector
load_init_vect :in std_logic;
......@@ -1809,9 +1806,6 @@ package can_components is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......@@ -2076,9 +2070,6 @@ package can_components is
-- Unit is receiver
is_receiver :in std_logic;
-- Unit is idle
is_idle :in std_logic;
-- Loss of arbitration -> Turn receiver!
arbitration_lost :out std_logic;
......@@ -3351,9 +3342,6 @@ package can_components is
-----------------------------------------------------------------------
-- Segment end (either due to re-sync, or reaching expected length)
segm_end : in std_logic;
-- Hard synchronisation is valid
h_sync_valid : in std_logic;
-- CTU CAN FD is enabled
drv_ena : in std_logic;
......
......@@ -133,10 +133,6 @@ package cmn_lib is
component endian_swapper is
generic (
-- If true, "swap_in" signal selects between swapping/non-swapping.
-- If false "swap_gen" generic selects bewtween swapping/non-swapping.
G_SWAP_BY_SIGNAL : boolean := false;
-- When true, output word is endian swapped as long as "swap_by_signal"
-- is true. Otherwise it has no meaning.
G_SWAP_GEN : boolean := false;
......@@ -152,11 +148,7 @@ package cmn_lib is
input : in std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Data output
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0);
-- Swap signal (used only when "swap_by_signal=true")
-- Swaps endian when '1', keeps otherwise.
swap_in : in std_logic
output : out std_logic_vector(G_WORD_SIZE * G_GROUP_SIZE - 1 downto 0)
);
end component;
......
......@@ -280,6 +280,8 @@ architecture rtl of memory_registers is
constant C_NOT_RESET_POLARITY : std_logic := not G_RESET_POLARITY;
signal ewl_padded : std_logic_vector(8 downto 0);
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
......@@ -480,12 +482,14 @@ begin
'1' when (is_idle = '1') else
'0';
ewl_padded <= '0' & control_registers_out.ewl(7 downto 0);
status_comb(EWL_IND) <=
'1' when to_integer(unsigned(control_registers_out.ewl)) <=
to_integer(unsigned(stat_bus(STAT_TX_COUNTER_HIGH downto STAT_TX_COUNTER_LOW)))
'1' when unsigned(ewl_padded) <=
unsigned(stat_bus(STAT_TX_COUNTER_HIGH downto STAT_TX_COUNTER_LOW))
else
'1' when to_integer(unsigned(control_registers_out.ewl)) <=
to_integer(unsigned(stat_bus(STAT_RX_COUNTER_HIGH downto STAT_RX_COUNTER_LOW)))
'1' when unsigned(ewl_padded) <=
unsigned(stat_bus(STAT_RX_COUNTER_HIGH downto STAT_RX_COUNTER_LOW))
else
'0';
......
......@@ -86,9 +86,6 @@ entity bit_time_fsm is
-----------------------------------------------------------------------
-- Segment end (either due to re-sync, or reaching expected length)
segm_end : in std_logic;
-- Hard synchronisation is valid
h_sync_valid : in std_logic;
-- CTU CAN FD is enabled
drv_ena : in std_logic;
......@@ -127,7 +124,7 @@ begin
----------------------------------------------------------------------------
-- Next state process (combinational)
----------------------------------------------------------------------------
next_state_proc : process(current_state, h_sync_valid, segm_end, drv_ena)
next_state_proc : process(current_state, segm_end, drv_ena)
begin
next_state <= current_state;
......
......@@ -444,7 +444,6 @@ begin
clk_sys => clk_sys, -- IN
res_n => res_n, -- IN
segm_end => segment_end, -- IN
h_sync_valid => h_sync_valid, -- IN
drv_ena => drv_ena, -- IN
is_tseg1 => is_tseg1, -- OUT
is_tseg2 => is_tseg2, -- OUT
......
......@@ -295,7 +295,6 @@ begin
crc_enable => enable,
crc_spec_enable => '0',
crc_calc_from_rx => '0',
is_receiver => '0',
load_init_vect => load_init_vect,
-- CRC Outputs
......
......@@ -206,7 +206,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Operation control FSM Interface
signal is_transmitter_1 : std_logic := '1';
signal is_receiver_1 : std_logic := '0';
signal is_idle_1 : std_logic := '0';
signal arbitration_lost_1 : std_logic;
signal set_transmitter_1 : std_logic;
signal set_receiver_1 : std_logic;
......@@ -320,7 +319,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Operation control FSM Interface
signal is_transmitter_2 : std_logic := '0';
signal is_receiver_2 : std_logic := '1';
signal is_idle_2 : std_logic := '0';
signal arbitration_lost_2 : std_logic;
signal set_transmitter_2 : std_logic;
signal set_receiver_2 : std_logic;
......@@ -717,7 +715,6 @@ begin
-- Operation control FSM Interface
is_transmitter => is_transmitter_1,
is_receiver => is_receiver_1,
is_idle => is_idle_1,
arbitration_lost => arbitration_lost_1,
set_transmitter => set_transmitter_1,
set_receiver => set_receiver_1,
......@@ -839,7 +836,6 @@ begin
-- Operation control FSM Interface
is_transmitter => is_transmitter_2,
is_receiver => is_receiver_2,
is_idle => is_idle_2,
arbitration_lost => arbitration_lost_2,
set_transmitter => set_transmitter_2,
set_receiver => set_receiver_2,
......
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