Skip to content
GitLab
Projects
Groups
Snippets
Help
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
C
CTU CAN FD IP Core
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
14
Issues
14
List
Boards
Labels
Service Desk
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Operations
Operations
Incidents
Environments
Packages & Registries
Packages & Registries
Container Registry
Analytics
Analytics
CI / CD
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
canbus
CTU CAN FD IP Core
Commits
53e41a29
Commit
53e41a29
authored
Mar 06, 2020
by
Ille, Ondrej, Ing.
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
src,test: Second batch of Vivado synthesis warnings.
parent
6e22a934
Changes
12
Hide whitespace changes
Inline
Side-by-side
Showing
12 changed files
with
23 additions
and
81 deletions
+23
-81
src/can_core/can_core.vhd
src/can_core/can_core.vhd
+0
-2
src/can_core/can_crc.vhd
src/can_core/can_crc.vhd
+0
-3
src/can_core/protocol_control.vhd
src/can_core/protocol_control.vhd
+1
-7
src/can_core/protocol_control_fsm.vhd
src/can_core/protocol_control_fsm.vhd
+0
-3
src/common/endian_swapper.vhd
src/common/endian_swapper.vhd
+12
-31
src/lib/can_components.vhd
src/lib/can_components.vhd
+0
-12
src/lib/cmn_lib.vhd
src/lib/cmn_lib.vhd
+1
-9
src/memory_registers/memory_registers.vhd
src/memory_registers/memory_registers.vhd
+8
-4
src/prescaler/bit_time_fsm.vhd
src/prescaler/bit_time_fsm.vhd
+1
-4
src/prescaler/prescaler.vhd
src/prescaler/prescaler.vhd
+0
-1
test/unit/CRC/CRC_tb.vhd
test/unit/CRC/CRC_tb.vhd
+0
-1
test/unit/Protocol_Control/Protocol_Control_tb.vhd
test/unit/Protocol_Control/Protocol_Control_tb.vhd
+0
-4
No files found.
src/can_core/can_core.vhd
View file @
53e41a29
...
...
@@ -519,7 +519,6 @@ begin
-- Operation control FSM Interface
is_transmitter
=>
is_transmitter
,
-- IN
is_receiver
=>
is_receiver
,
-- IN
is_idle
=>
is_idle
,
-- IN
arbitration_lost
=>
arbitration_lost_i
,
-- OUT
set_transmitter
=>
set_transmitter
,
-- OUT
set_receiver
=>
set_receiver
,
-- OUT
...
...
@@ -702,7 +701,6 @@ begin
crc_enable
=>
crc_enable
,
-- IN
crc_spec_enable
=>
crc_spec_enable
,
-- IN
crc_calc_from_rx
=>
crc_calc_from_rx
,
-- IN
is_receiver
=>
is_receiver
,
-- IN
load_init_vect
=>
load_init_vect
,
-- IN
-- CRC Outputs
...
...
src/can_core/can_crc.vhd
View file @
53e41a29
...
...
@@ -146,9 +146,6 @@ entity can_crc is
-- Use RX Data for CRC calculation
crc_calc_from_rx
:
in
std_logic
;
-- Unit is receiver of a frame
is_receiver
:
in
std_logic
;
-- Load CRC Initialization vector
load_init_vect
:
in
std_logic
;
...
...
src/can_core/protocol_control.vhd
View file @
53e41a29
...
...
@@ -231,9 +231,6 @@ entity protocol_control is
-- Unit is receiver
is_receiver
:
in
std_logic
;
-- Unit is idle
is_idle
:
in
std_logic
;
-- Loss of arbitration -> Turn receiver!
arbitration_lost
:
out
std_logic
;
...
...
@@ -635,15 +632,13 @@ begin
---------------------------------------------------------------------------
endian_swapper_tx_inst
:
endian_swapper
generic
map
(
G_SWAP_BY_SIGNAL
=>
false
,
G_SWAP_GEN
=>
true
,
G_WORD_SIZE
=>
4
,
-- Number of Groups
G_GROUP_SIZE
=>
8
-- Group size (bits)
)
port
map
(
input
=>
tran_word
,
-- IN
output
=>
tran_word_swapped
,
-- OUT
swap_in
=>
'0'
-- IN
output
=>
tran_word_swapped
-- OUT
);
...
...
@@ -780,7 +775,6 @@ begin
-- Operation control interface
is_transmitter
=>
is_transmitter
,
-- IN
is_receiver
=>
is_receiver
,
-- IN
is_idle
=>
is_idle
,
-- IN
arbitration_lost
=>
arbitration_lost_i
,
-- OUT
set_transmitter
=>
set_transmitter
,
-- OUT
set_receiver
=>
set_receiver
,
-- OUT
...
...
src/can_core/protocol_control_fsm.vhd
View file @
53e41a29
...
...
@@ -427,9 +427,6 @@ entity protocol_control_fsm is
-- Unit is receiver
is_receiver
:
in
std_logic
;
-- Unit is idle
is_idle
:
in
std_logic
;
-- Loss of arbitration -> Turn receiver!
arbitration_lost
:
out
std_logic
;
...
...
src/common/endian_swapper.vhd
View file @
53e41a29
...
...
@@ -68,11 +68,7 @@ use work.CAN_FD_frame_format.all;
entity
endian_swapper
is
generic
(
-- If true, "swap_in" signal selects between swapping/non-swapping.
-- If false "swap_gen" generic selects bewtween swapping/non-swapping.
G_SWAP_BY_SIGNAL
:
boolean
:
=
false
;
-- When true, output word is endian swapped as long as "swap_by_signal"
-- is true. Otherwise it has no meaning.
G_SWAP_GEN
:
boolean
:
=
false
;
...
...
@@ -88,11 +84,7 @@ entity endian_swapper is
input
:
in
std_logic_vector
(
G_WORD_SIZE
*
G_GROUP_SIZE
-
1
downto
0
);
-- Data output
output
:
out
std_logic_vector
(
G_WORD_SIZE
*
G_GROUP_SIZE
-
1
downto
0
);
-- Swap signal (used only when "swap_by_signal=true")
-- Swaps endian when '1', keeps otherwise.
swap_in
:
in
std_logic
output
:
out
std_logic_vector
(
G_WORD_SIZE
*
G_GROUP_SIZE
-
1
downto
0
)
);
end
entity
;
...
...
@@ -123,30 +115,19 @@ begin
input
(
u_ind_orig
downto
l_ind_orig
);
end
loop
;
end
process
;
---------------------------------------------------------------------------
-- Swapping by generic
---------------------------------------------------------------------------
swap_by_generic_gen
:
if
(
not
G_SWAP_BY_SIGNAL
)
generate
-- Swap
swap_by_generic_true_gen
:
if
(
G_SWAP_GEN
)
generate
output
<=
swapped
;
end
generate
swap_by_generic_true_gen
;
-- Don't Swap
swap_by_generic_false_gen
:
if
(
not
G_SWAP_GEN
)
generate
output
<=
input
;
end
generate
swap_by_generic_false_gen
;
end
generate
swap_by_generic_gen
;
-- Swap
swap_by_generic_true_gen
:
if
(
G_SWAP_GEN
)
generate
output
<=
swapped
;
end
generate
swap_by_generic_true_gen
;
---------------------------------------------------------------------------
-- Swapping by input
---------------------------------------------------------------------------
swap_by_input_gen
:
if
(
G_SWAP_BY_SIGNAL
)
generate
output
<=
swapped
when
(
swap_in
=
'1'
)
else
input
;
end
generate
swap_by_input_gen
;
-- Don't Swap
swap_by_generic_false_gen
:
if
(
not
G_SWAP_GEN
)
generate
output
<=
input
;
end
generate
swap_by_generic_false_gen
;
end
architecture
;
src/lib/can_components.vhd
View file @
53e41a29
...
...
@@ -792,9 +792,6 @@ package can_components is
-- Use RX Data for CRC calculation
crc_calc_from_rx
:
in
std_logic
;
-- Unit is receiver of a frame
is_receiver
:
in
std_logic
;
-- Load CRC Initialization vector
load_init_vect
:
in
std_logic
;
...
...
@@ -1809,9 +1806,6 @@ package can_components is
-- Unit is receiver
is_receiver
:
in
std_logic
;
-- Unit is idle
is_idle
:
in
std_logic
;
-- Loss of arbitration -> Turn receiver!
arbitration_lost
:
out
std_logic
;
...
...
@@ -2076,9 +2070,6 @@ package can_components is
-- Unit is receiver
is_receiver
:
in
std_logic
;
-- Unit is idle
is_idle
:
in
std_logic
;
-- Loss of arbitration -> Turn receiver!
arbitration_lost
:
out
std_logic
;
...
...
@@ -3351,9 +3342,6 @@ package can_components is
-----------------------------------------------------------------------
-- Segment end (either due to re-sync, or reaching expected length)
segm_end
:
in
std_logic
;
-- Hard synchronisation is valid
h_sync_valid
:
in
std_logic
;
-- CTU CAN FD is enabled
drv_ena
:
in
std_logic
;
...
...
src/lib/cmn_lib.vhd
View file @
53e41a29
...
...
@@ -133,10 +133,6 @@ package cmn_lib is
component
endian_swapper
is
generic
(
-- If true, "swap_in" signal selects between swapping/non-swapping.
-- If false "swap_gen" generic selects bewtween swapping/non-swapping.
G_SWAP_BY_SIGNAL
:
boolean
:
=
false
;
-- When true, output word is endian swapped as long as "swap_by_signal"
-- is true. Otherwise it has no meaning.
G_SWAP_GEN
:
boolean
:
=
false
;
...
...
@@ -152,11 +148,7 @@ package cmn_lib is
input
:
in
std_logic_vector
(
G_WORD_SIZE
*
G_GROUP_SIZE
-
1
downto
0
);
-- Data output
output
:
out
std_logic_vector
(
G_WORD_SIZE
*
G_GROUP_SIZE
-
1
downto
0
);
-- Swap signal (used only when "swap_by_signal=true")
-- Swaps endian when '1', keeps otherwise.
swap_in
:
in
std_logic
output
:
out
std_logic_vector
(
G_WORD_SIZE
*
G_GROUP_SIZE
-
1
downto
0
)
);
end
component
;
...
...
src/memory_registers/memory_registers.vhd
View file @
53e41a29
...
...
@@ -280,6 +280,8 @@ architecture rtl of memory_registers is
constant
C_NOT_RESET_POLARITY
:
std_logic
:
=
not
G_RESET_POLARITY
;
signal
ewl_padded
:
std_logic_vector
(
8
downto
0
);
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
...
...
@@ -480,12 +482,14 @@ begin
'1'
when
(
is_idle
=
'1'
)
else
'0'
;
ewl_padded
<=
'0'
&
control_registers_out
.
ewl
(
7
downto
0
);
status_comb
(
EWL_IND
)
<=
'1'
when
to_integer
(
unsigned
(
control_registers_out
.
ewl
)
)
<=
to_integer
(
unsigned
(
stat_bus
(
STAT_TX_COUNTER_HIGH
downto
STAT_TX_COUNTER_LOW
)
))
'1'
when
unsigned
(
ewl_padded
)
<=
unsigned
(
stat_bus
(
STAT_TX_COUNTER_HIGH
downto
STAT_TX_COUNTER_LOW
))
else
'1'
when
to_integer
(
unsigned
(
control_registers_out
.
ewl
)
)
<=
to_integer
(
unsigned
(
stat_bus
(
STAT_RX_COUNTER_HIGH
downto
STAT_RX_COUNTER_LOW
)
))
'1'
when
unsigned
(
ewl_padded
)
<=
unsigned
(
stat_bus
(
STAT_RX_COUNTER_HIGH
downto
STAT_RX_COUNTER_LOW
))
else
'0'
;
...
...
src/prescaler/bit_time_fsm.vhd
View file @
53e41a29
...
...
@@ -86,9 +86,6 @@ entity bit_time_fsm is
-----------------------------------------------------------------------
-- Segment end (either due to re-sync, or reaching expected length)
segm_end
:
in
std_logic
;
-- Hard synchronisation is valid
h_sync_valid
:
in
std_logic
;
-- CTU CAN FD is enabled
drv_ena
:
in
std_logic
;
...
...
@@ -127,7 +124,7 @@ begin
----------------------------------------------------------------------------
-- Next state process (combinational)
----------------------------------------------------------------------------
next_state_proc
:
process
(
current_state
,
h_sync_valid
,
segm_end
,
drv_ena
)
next_state_proc
:
process
(
current_state
,
segm_end
,
drv_ena
)
begin
next_state
<=
current_state
;
...
...
src/prescaler/prescaler.vhd
View file @
53e41a29
...
...
@@ -444,7 +444,6 @@ begin
clk_sys
=>
clk_sys
,
-- IN
res_n
=>
res_n
,
-- IN
segm_end
=>
segment_end
,
-- IN
h_sync_valid
=>
h_sync_valid
,
-- IN
drv_ena
=>
drv_ena
,
-- IN
is_tseg1
=>
is_tseg1
,
-- OUT
is_tseg2
=>
is_tseg2
,
-- OUT
...
...
test/unit/CRC/CRC_tb.vhd
View file @
53e41a29
...
...
@@ -295,7 +295,6 @@ begin
crc_enable
=>
enable
,
crc_spec_enable
=>
'0'
,
crc_calc_from_rx
=>
'0'
,
is_receiver
=>
'0'
,
load_init_vect
=>
load_init_vect
,
-- CRC Outputs
...
...
test/unit/Protocol_Control/Protocol_Control_tb.vhd
View file @
53e41a29
...
...
@@ -206,7 +206,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Operation control FSM Interface
signal
is_transmitter_1
:
std_logic
:
=
'1'
;
signal
is_receiver_1
:
std_logic
:
=
'0'
;
signal
is_idle_1
:
std_logic
:
=
'0'
;
signal
arbitration_lost_1
:
std_logic
;
signal
set_transmitter_1
:
std_logic
;
signal
set_receiver_1
:
std_logic
;
...
...
@@ -320,7 +319,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Operation control FSM Interface
signal
is_transmitter_2
:
std_logic
:
=
'0'
;
signal
is_receiver_2
:
std_logic
:
=
'1'
;
signal
is_idle_2
:
std_logic
:
=
'0'
;
signal
arbitration_lost_2
:
std_logic
;
signal
set_transmitter_2
:
std_logic
;
signal
set_receiver_2
:
std_logic
;
...
...
@@ -717,7 +715,6 @@ begin
-- Operation control FSM Interface
is_transmitter
=>
is_transmitter_1
,
is_receiver
=>
is_receiver_1
,
is_idle
=>
is_idle_1
,
arbitration_lost
=>
arbitration_lost_1
,
set_transmitter
=>
set_transmitter_1
,
set_receiver
=>
set_receiver_1
,
...
...
@@ -839,7 +836,6 @@ begin
-- Operation control FSM Interface
is_transmitter
=>
is_transmitter_2
,
is_receiver
=>
is_receiver_2
,
is_idle
=>
is_idle_2
,
arbitration_lost
=>
arbitration_lost_2
,
set_transmitter
=>
set_transmitter_2
,
set_receiver
=>
set_receiver_2
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment