Commit 53559441 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added Memory registers diagram. Modified documentation.

parent 133de787
......@@ -533,7 +533,7 @@ Ille Ondrej, Martin Jeřábek
\noindent
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......@@ -696,7 +696,7 @@ Updated register map description, external references to generated maps.
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......@@ -705,7 +705,7 @@ Updated register map description, external references to generated maps.
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......@@ -714,7 +714,7 @@ Martin Jerabek
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......@@ -723,13 +723,52 @@ Martin Jerabek
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Added Linux driver description
\end_layout
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2.1.1
\end_layout
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</cell>
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Ondrej Ille
\end_layout
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12-2018
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Added Register map block diagram after re-implementation of registers via
Register map generator.
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......@@ -1182,21 +1221,17 @@ doc/core/registerMap.lyx
).
\end_layout
\begin_layout Itemize
RTL Code of Control Registers module and Event Logger Registers module.
\end_layout
\begin_layout Standard
To generate these design materials CTU CAN FD IP Core contains its own IP-XACT
generator framework (located under
\begin_inset Quotes eld
\end_inset
scripts/pyXact_generator
\begin_inset Quotes erd
\end_inset
) which extends the implementation of
generator which can be found at
\begin_inset CommandInset href
LatexCommand href
name "olofk/ipyxact"
target "https://github.com/olofk/ipyxact"
name "regmap_gen"
target "https://github.com/Blebowski/Reg_Map_Gen"
literal "false"
\end_inset
......@@ -13110,6 +13145,13 @@ name "fig:TXT_Buffer-FSM"
\end_inset
\end_layout
\begin_layout Standard
\begin_inset Newpage pagebreak
\end_inset
\end_layout
\begin_layout Subsection
......@@ -13144,10 +13186,26 @@ canfd_registers
\begin_layout Standard
Memory Registers provide an interface between SoC Memory Bus (Avalon or
APB) and all control and Status signals of CTU CAN FD IP function.
Address decoder for access to TXT Buffers is implemented in this module.
Driving bus assignments are implemented in this module.
Register structure is in described in Chapter:
APB) and all control and status signals of CTU CAN FD IP function.
Memory registers consist of two separate modules: Control registers and
Event Loger Registers.
Each module is generated by Register map generator Tool which is further
described in
\begin_inset Flex URL
status open
\begin_layout Plain Layout
https://github.com/Blebowski/Reg_Map_Gen
\end_layout
\end_inset
.
Outputs of Register modules are connected to Driving Bus.
Inputs to Register modules (corresponding to read-only registers) are driven
from Status Bus.
Block diagram is shown in
\begin_inset ERT
status open
......@@ -13155,15 +13213,71 @@ status open
\backslash
hyperref[3.
CAN FD Core memory map]{3.
CAN FD Core memory map}
hyperref[fig:Memory_regs-block-diagram]{Figure }
\end_layout
\end_inset
\begin_inset CommandInset ref
LatexCommand ref
reference "fig:Memory_regs-block-diagram"
plural "false"
caps "false"
noprefix "false"
\end_inset
.
Frame Format in TXT Buffers and RX Buffer is described in Chapter:
\end_layout
\begin_layout Standard
\begin_inset Float figure
placement h
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/Memory_regs_block_diagram.pdf
lyxscale 20
scale 70
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption Standard
\begin_layout Plain Layout
Memory registers block diagram
\begin_inset CommandInset label
LatexCommand label
name "fig:Memory_regs-block-diagram"
\end_inset
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Standard
Register structure is in described in Chapter:
\begin_inset ERT
status open
......@@ -13171,14 +13285,14 @@ status open
\backslash
hyperref[4.
CAN FD frame format]{4.
CAN FD frame format}
hyperref[3.
CAN FD Core memory map]{3.
CAN FD Core memory map}
\end_layout
\end_inset
.
\end_layout
\begin_layout Standard
......
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