Commit 5313e085 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Add forgotten driver to prev_sample.

parent d94c6a1c
Pipeline #6680 passed with stages
in 13 minutes and 16 seconds
......@@ -170,5 +170,8 @@ begin
insert_pipeline_false_gen : if (pipeline_sampled_data = false) generate
data_rx <= rx_data_i;
end generate insert_pipeline_false_gen;
-- Internal signal to output propagation
prev_sample <= sample_prev_q;
end architecture;
\ No newline at end of file
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