Commit 5313307a authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added randomization to rest of unit tests.

Formatted unit tests after modifications to
be readable properly...
parent aeae2020
Pipeline #1164 passed with stages
in 1 minute and 16 seconds
......@@ -767,6 +767,7 @@ begin
log("Restarting Bit stuffing-destuffing test!", info_l, log_level);
wait for 5 ns;
reset_test(res_n, status, run, stat_err_ctr);
apply_rand_seed(seed, 0, rand_ctr);
log("Restarted Bit stuffing-destuffing test", info_l, log_level);
print_test_info(iterations, log_level, error_beh, error_tol);
......
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......@@ -187,7 +187,7 @@ architecture Event_logger_unit_test of CAN_test is
signal clk_sys :in std_logic;
signal log_state :in logger_state_type;
signal trig_inputs :in std_logic_vector(trig_amount - 1 downto 0);
signal drv_trig :in std_logic_vector(trig_amount - 1 downto 0);
signal drv_trig :in std_logic_vector(trig_amount - 1 downto 0);
signal log_level :in log_lvl_type;
variable outcome :inout boolean
) is
......@@ -269,7 +269,10 @@ architecture Event_logger_unit_test of CAN_test is
end procedure;
begin
----------------------------------------------------------------------------
-- DUT
----------------------------------------------------------------------------
CAN_logger_comp : CAN_logger
generic map(
memory_size => 16 --Only 2^k possible!
......@@ -369,6 +372,7 @@ begin
trig_inputs(T_TRS_IND) <= evnt_inputs(C_TRS_IND);
trig_inputs(T_CRCS_IND) <= evnt_inputs(C_CRCS_IND);
----------------------------------------------------------------------------
-- Generation of random events. Is completely not synced with event logger
-- generation.
......@@ -379,6 +383,10 @@ begin
begin
wait until rising_edge(clk_sys);
if (res_n = ACT_RESET) then
apply_rand_seed(seed, 1, rand_ctr_2);
end if;
-- Generate random events
rand_logic_vect_s(rand_ctr_2, evnt_inputs, 0.1);
......@@ -494,6 +502,7 @@ begin
errors <= error_ctr;
----------------------------------------------------------------------------
-- Main test process
----------------------------------------------------------------------------
......@@ -504,6 +513,7 @@ begin
log("Restarting Event logget unit test!", info_l, log_level);
wait for 5 ns;
reset_test(res_n, status, run, error_ctr);
apply_rand_seed(seed, 0, rand_ctr);
log("Restarted Event logget unit test", info_l, log_level);
print_test_info(iterations, log_level, error_beh, error_tol);
......@@ -552,7 +562,7 @@ end architecture;
architecture Event_logger_unit_test_wrapper of CAN_test_wrapper is
--Select architecture of the test
-- Select architecture of the test
for test_comp : CAN_test use entity work.CAN_test(Event_logger_unit_test);
signal run : boolean;
......@@ -573,7 +583,6 @@ begin
status => status_int,
errors => errors
);
status <= status_int;
......
This diff is collapsed.
......@@ -518,7 +518,7 @@ begin
end if;
else
--TODO...
report "Only NOMINAL and DATA sampling is supported" severity error;
end if;
end process;
......@@ -604,6 +604,9 @@ begin
variable sync_time : integer;
variable skip_sync : boolean;
begin
if (res_n = ACT_RESET) then
apply_rand_seed(seed, 1, rand_ctr_sync_edge);
end if;
-- Generate parameters for new resynchronisation
wait until falling_edge(clk_sys) and bt_FSM_out = sync;
......@@ -689,7 +692,8 @@ begin
-- Generates random initial bit time settings to avoid having zero
-- values on the input of DUT after reset!
gen_bit_time_setting(rand_ctr, setting);
apply_rand_seed(seed, 0, rand_ctr);
gen_bit_time_setting(rand_ctr, setting);
reset_test(res_n, status, run, main_err_ctr);
log("Restarted Prescaler unit test", info_l, log_level);
......
......@@ -1159,6 +1159,7 @@ begin
log("Restarting Protocol control unit test!", info_l, log_level);
wait for 5 ns;
reset_test(res_n, status, run, error_ctr);
apply_rand_seed(seed, 0, rand_ctr);
log("Restarted Protocol control unit test", info_l, log_level);
print_test_info(iterations, log_level, error_beh, error_tol);
......
......@@ -585,6 +585,7 @@ begin
log("Restarting RX Buffer test!", info_l, log_level);
wait for 5 ns;
reset_test(res_n, status, run, stim_errs);
apply_rand_seed(seed, 0, rand_ctr);
log("Restarted RX Bufrer test", info_l, log_level);
print_test_info(iterations, log_level, error_beh, error_tol);
......@@ -651,6 +652,10 @@ begin
wait for 5 ns;
end if;
if (res_n = ACT_RESET) then
apply_rand_seed(seed, 1, rand_ctr_3);
end if;
------------------------------------------------------------------------
-- Read frames as long as Output memory is not filled. Wait random time
-- in between, to allow for data overrun to occur!
......
......@@ -206,7 +206,7 @@ architecture tx_buf_unit_test of CAN_test is
begin
----------------------------------------------------------------------------
-- Buffer components - create only one instance
-- DUT - Create only one buffer instance
----------------------------------------------------------------------------
txt_Buf_comp : txtBuffer
generic map(
......@@ -228,28 +228,30 @@ begin
txt_addr => txt_addr,
txt_buf_ready => txt_buf_ready
);
---------------------------------
----------------------------------------------------------------------------
-- Clock generation
---------------------------------
----------------------------------------------------------------------------
clock_gen : process
variable period : natural := f100_Mhz;
variable duty : natural := 50;
variable epsilon : natural := 0;
variable period : natural := f100_Mhz;
variable duty : natural := 50;
variable epsilon : natural := 0;
begin
generate_clock(period, duty, epsilon, clk_sys);
generate_clock(period, duty, epsilon, clk_sys);
end process;
--------------------------------------------
----------------------------------------------------------------------------
-- Data generation - stored by user writes
--------------------------------------------
----------------------------------------------------------------------------
data_gen_proc : process
variable buf_fsm : txt_fsm_type;
begin
tran_cs <= '0';
while res_n = ACT_RESET loop
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
apply_rand_seed(seed, 3, rand_gen_ctr);
end loop;
-- Generate random address and data and attempt to store it
......@@ -279,18 +281,18 @@ begin
tran_cs <= '0';
wait until rising_edge(clk_sys);
end process;
---------------------------------------------
----------------------------------------------------------------------------
-- Reading the data like as If from CAN Core
---------------------------------------------
----------------------------------------------------------------------------
data_read_proc : process
variable tmp : std_logic_vector(4 downto 0);
begin
while res_n = ACT_RESET loop
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
apply_rand_seed(seed, 2, rand_read_ctr);
end loop;
data_coh_err_ctr <= 0;
......@@ -314,15 +316,16 @@ begin
end process;
---------------------------------------------------------
----------------------------------------------------------------------------
-- Sending random commands to the buffer from SW and HW
---------------------------------------------------------
----------------------------------------------------------------------------
commands_proc : process
variable tmp_real : real;
begin
while res_n = ACT_RESET loop
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
apply_rand_seed(seed, 1, rand_com_gen_ctr);
end loop;
wait until falling_edge(clk_sys);
......@@ -359,7 +362,7 @@ begin
rand_logic_s(rand_com_gen_ctr, txt_sw_cmd.set_rdy, 0.2);
rand_logic_s(rand_com_gen_ctr, txt_sw_cmd.set_ety, 0.2);
rand_logic_s(rand_com_gen_ctr, txt_sw_cmd.set_abt, 0.2);
wait for 0 ns;
wait for 0 ns;
-- Calculate the expected state
calc_exp_state(txt_sw_cmd, txt_hw_cmd, txtb_state, txtb_exp_state);
......@@ -375,8 +378,8 @@ begin
error_l, log_level);
end if;
-- Set all the commands to be inactive
txt_hw_cmd.valid <= '0';
-- Set all the commands to be inactive
txt_hw_cmd.valid <= '0';
txt_hw_cmd.err <= '0';
txt_hw_cmd.arbl <= '0';
txt_hw_cmd.failed <= '0';
......@@ -388,11 +391,12 @@ begin
end process;
---------------------------------
---------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Main Test process
---------------------------------
---------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
test_proc : process
variable rand_nr : real;
variable rand_time : time;
......@@ -400,6 +404,7 @@ begin
log("Restarting TXT Buffer test!", info_l, log_level);
wait for 5 ns;
reset_test(res_n, status, run, error_ctr);
apply_rand_seed(seed, 0, rand_ctr);
log("Restarted TXT Buffer test", info_l, log_level);
print_test_info(iterations, log_level, error_beh, error_tol);
......@@ -438,9 +443,9 @@ end architecture;
--------------------------------------------------------------------------------
architecture tx_buf_unit_test_wrapper of CAN_test_wrapper is
--Select architecture of the test
for test_comp : CAN_test use entity work.CAN_test(tx_buf_unit_test);
-- Select architecture of the test
for test_comp : CAN_test use entity work.CAN_test(tx_buf_unit_test);
-- Input trigger, test starts running when true
signal run : boolean;
......@@ -450,38 +455,37 @@ architecture tx_buf_unit_test_wrapper of CAN_test_wrapper is
-- Amount of errors which appeared in the test
signal errors : natural;
begin
-- In this test wrapper generics are directly connected to the signals
-- of test entity
test_comp : CAN_test
port map(
run => run,
--iterations => 10000,
iterations => iterations ,
log_level => log_level,
error_beh => error_beh,
error_tol => error_tol,
status => status_int,
errors => errors
);
-- In this test wrapper generics are directly connected to the signals
-- of test entity
test_comp : CAN_test
port map(
run => run,
iterations => iterations ,
log_level => log_level,
error_beh => error_beh,
error_tol => error_tol,
status => status_int,
errors => errors
);
status <= status_int;
status <= status_int;
------------------------------------
-- Starts the test and lets it run
------------------------------------
test : process
begin
run <= true;
wait for 1 ns;
-- Wait until the only test finishes and then propagate the results
wait until (status_int = passed or status_int = failed);
wait for 100 ns;
run <= false;
end process;
----------------------------------------------------------------------------
-- Starts the test and lets it run
----------------------------------------------------------------------------
test : process
begin
run <= true;
wait for 1 ns;
-- Wait until the only test finishes and then propagate the results
wait until (status_int = passed or status_int = failed);
wait for 100 ns;
run <= false;
end process;
end;
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