Commit 501a8536 authored by Pavel Pisa's avatar Pavel Pisa

Merge branch '226-without-vhdl-2008-try-2' into 'master'

Resolve VHDL 2008 is not supported in Vivado IP packager still .

Closes #226

See merge request illeondr/CAN_FD_IP_Core!188
parents 377b0be7 0b8b1a18
Pipeline #5743 passed with stages
in 13 minutes and 1 second
#!/bin/sh
SCRIP_DIR="$(cd "$0" ; pwd)"
cd "$SCRIP_DIR"
python3 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml \
--updVHDLPackage True --updHeaderFile True --updLyxDocs True --updRTLRegMap True || exit 1
( cd ../src/memory_registers/generated ; patch < "$SCRIP_DIR/memory_reg.vhd.diff" ) || exit 1
diff memory_reg.vhd generated/memory_reg.vhd
index 1da3851..3778de0 100644
--- generated/memory_reg.vhd
+++ generated/memory_reg.vhd
@@ -46,17 +46,17 @@ entity memory_reg is
-- Data mask. Each logic 1 indicates present bit, logic 0 indicates
-- reserved bit in register bits. Reserved bit always returns 0.
- constant data_mask : std_logic_vector(data_width - 1 downto 0);
+ constant data_mask : std_logic_vector;
-- Reset polarity
constant reset_polarity : std_logic := '0';
-- Reset value of register
- constant reset_value : std_logic_vector(data_width - 1 downto 0);
+ constant reset_value : std_logic_vector;
-- If given bit of the register should be cleared automatically one
-- clock cycle after writing.
- constant auto_clear : std_logic_vector(data_width - 1 downto 0)
+ constant auto_clear : std_logic_vector
);
port(
------------------------------------------------------------------------
@@ -84,6 +84,17 @@ end entity memory_reg;
architecture rtl of memory_reg is
+ pure function bit_in_mask(mask_vec: std_logic_vector; bit_pos : natural)
+ return std_ulogic is
+ begin
+ if mask_vec'ascending then
+ return mask_vec(mask_vec'length - 1 - bit_pos);
+ else
+ return mask_vec(bit_pos);
+ end if;
+ --return mask_vec(bit_pos);
+ end function bit_in_mask;
+
-- Register implementation itself!
signal reg_value_r : std_logic_vector(data_width - 1 downto 0);
@@ -112,16 +123,16 @@ begin
-- Register instance
----------------------------------------------------------------------------
bit_gen : for i in 0 to data_width - 1 generate
-
+
------------------------------------------------------------------------
-- Register implementation itself
------------------------------------------------------------------------
- reg_present_gen : if (data_mask(i) = '1') generate
+ reg_present_gen : if (bit_in_mask(data_mask, i) = '1') generate
reg_access_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
- reg_value_r(i) <= reset_value(i);
+ reg_value_r(i) <= bit_in_mask(reset_value, i);
elsif (rising_edge(clk_sys)) then
@@ -131,8 +142,9 @@ begin
-- Clear the register if autoclear is set and register is
-- set
- elsif (auto_clear(i) = '1' and reg_value_r(i) = '1') then
- reg_value_r(i) <= reset_value(i);
+ elsif (bit_in_mask(auto_clear, i) = '1' and
+ reg_value_r(i) = '1') then
+ reg_value_r(i) <= bit_in_mask(reset_value, i);
end if;
end if;
@@ -144,8 +156,8 @@ begin
-----------------------------------------------------------------------
-- Registers which are not present are stuck at reset value
-----------------------------------------------------------------------
- reg_not_present_gen : if (data_mask(i) = '0') generate
- reg_value_r(i) <= reset_value(i);
+ reg_not_present_gen : if (bit_in_mask(data_mask, i) = '0') generate
+ reg_value_r(i) <= bit_in_mask(reset_value, i);
end generate reg_not_present_gen;
end generate bit_gen;
......@@ -144,6 +144,8 @@ end entity;
architecture rtl of bit_stuffing is
signal data_out_int : std_logic;
---------------------------------------------------------------------------
-- Counter with number of equal consequent bits
---------------------------------------------------------------------------
......@@ -226,6 +228,8 @@ architecture rtl of bit_stuffing is
begin
data_out <= data_out_int;
---------------------------------------------------------------------------
-- Registering previous value of enable input to detect 0->1 transition.
---------------------------------------------------------------------------
......@@ -322,7 +326,7 @@ begin
---------------------------------------------------------------------------
same_bits_rst_trig <= '1' when (non_fix_to_fix_chng = '1') or
(stuff_lvl_reached = '1') or
(data_in /= data_out and fixed_stuff = '0')
(data_in /= data_out_int and fixed_stuff = '0')
else
'0';
......@@ -406,13 +410,13 @@ begin
-- 4. Keep previous value otherwise
---------------------------------------------------------------------------
data_out_nxt_ena <= RECESSIVE when (enable_prev = '0') else
(not data_out) when (tran_trig_1 = '1' and insert_stuff_bit = '1') else
(not data_out_int) when (tran_trig_1 = '1' and insert_stuff_bit = '1') else
data_in when (tran_trig_1 = '1') else
data_out;
data_out_int;
data_out_nxt <= data_out_nxt_ena when (enable = '1') else
data_in when (tran_trig_1 = '1') else
data_out;
data_out_int;
data_out_load <= '1' when (enable = '1' or tran_trig_1 = '1') else
'0';
......@@ -433,7 +437,7 @@ begin
input => data_out_nxt,
load => data_out_load,
output => data_out
output => data_out_int
);
......
......@@ -92,6 +92,9 @@ end entity;
architecture rtl of bus_traffic_counters is
signal tx_ctr_int : std_logic_vector(31 downto 0);
signal rx_ctr_int : std_logic_vector(31 downto 0);
-- Input selector
signal sel : std_logic;
......@@ -103,13 +106,16 @@ architecture rtl of bus_traffic_counters is
begin
tx_ctr <= tx_ctr_int;
rx_ctr <= rx_ctr_int;
-- Input selector
sel <= '1' when (inc_tx_ctr = '1') else
'0';
-- Multiplexor between TX and RX value to increment
sel_value <= tx_ctr when (sel = '1') else
rx_ctr;
sel_value <= tx_ctr_int when (sel = '1') else
rx_ctr_int;
-- Incremented value of either TX or RX counter
inc_value <= std_logic_vector(to_unsigned(
......@@ -121,11 +127,11 @@ begin
tx_ctr_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET or clear_tx_ctr = '1') then
tx_ctr <= (OTHERS => '0');
tx_ctr_int <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
if (inc_tx_ctr = '1') then
tx_ctr <= inc_value;
tx_ctr_int <= inc_value;
end if;
end if;
end process;
......@@ -137,11 +143,11 @@ begin
rx_ctr_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET or clear_rx_ctr = '1') then
rx_ctr <= (OTHERS => '0');
rx_ctr_int <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
if (inc_rx_ctr = '1') then
rx_ctr <= inc_value;
rx_ctr_int <= inc_value;
end if;
end if;
end process;
......
......@@ -46,17 +46,17 @@ entity memory_reg is
-- Data mask. Each logic 1 indicates present bit, logic 0 indicates
-- reserved bit in register bits. Reserved bit always returns 0.
constant data_mask : std_logic_vector(data_width - 1 downto 0);
constant data_mask : std_logic_vector;
-- Reset polarity
constant reset_polarity : std_logic := '0';
-- Reset value of register
constant reset_value : std_logic_vector(data_width - 1 downto 0);
constant reset_value : std_logic_vector;
-- If given bit of the register should be cleared automatically one
-- clock cycle after writing.
constant auto_clear : std_logic_vector(data_width - 1 downto 0)
constant auto_clear : std_logic_vector
);
port(
------------------------------------------------------------------------
......@@ -84,6 +84,17 @@ end entity memory_reg;
architecture rtl of memory_reg is
pure function bit_in_mask(mask_vec: std_logic_vector; bit_pos : natural)
return std_ulogic is
begin
if mask_vec'ascending then
return mask_vec(mask_vec'length - 1 - bit_pos);
else
return mask_vec(bit_pos);
end if;
--return mask_vec(bit_pos);
end function bit_in_mask;
-- Register implementation itself!
signal reg_value_r : std_logic_vector(data_width - 1 downto 0);
......@@ -112,16 +123,16 @@ begin
-- Register instance
----------------------------------------------------------------------------
bit_gen : for i in 0 to data_width - 1 generate
------------------------------------------------------------------------
-- Register implementation itself
------------------------------------------------------------------------
reg_present_gen : if (data_mask(i) = '1') generate
reg_present_gen : if (bit_in_mask(data_mask, i) = '1') generate
reg_access_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
reg_value_r(i) <= reset_value(i);
reg_value_r(i) <= bit_in_mask(reset_value, i);
elsif (rising_edge(clk_sys)) then
......@@ -131,8 +142,9 @@ begin
-- Clear the register if autoclear is set and register is
-- set
elsif (auto_clear(i) = '1' and reg_value_r(i) = '1') then
reg_value_r(i) <= reset_value(i);
elsif (bit_in_mask(auto_clear, i) = '1' and
reg_value_r(i) = '1') then
reg_value_r(i) <= bit_in_mask(reset_value, i);
end if;
end if;
......@@ -144,8 +156,8 @@ begin
-----------------------------------------------------------------------
-- Registers which are not present are stuck at reset value
-----------------------------------------------------------------------
reg_not_present_gen : if (data_mask(i) = '0') generate
reg_value_r(i) <= reset_value(i);
reg_not_present_gen : if (bit_in_mask(data_mask, i) = '0') generate
reg_value_r(i) <= bit_in_mask(reset_value, i);
end generate reg_not_present_gen;
end generate bit_gen;
......
......@@ -158,6 +158,13 @@ end entity;
architecture rtl of rx_buffer_pointers is
signal read_pointer_int : integer range 0 to buff_size - 1;
signal read_pointer_inc_1_int : integer range 0 to buff_size - 1;
signal write_pointer_int : integer range 0 to buff_size - 1;
signal write_pointer_raw_int : integer range 0 to buff_size - 1;
signal write_pointer_extra_ts_int : integer range 0 to buff_size - 1;
signal rx_mem_free_int_int : integer range 0 to buff_size + 1;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Driving bus signal aliases
......@@ -183,6 +190,12 @@ architecture rtl of rx_buffer_pointers is
signal rx_mem_free_int_inc_1 : integer range 0 to buff_size + 2;
begin
read_pointer <= read_pointer_int;
read_pointer_inc_1 <= read_pointer_inc_1_int;
write_pointer <= write_pointer_int;
write_pointer_raw <= write_pointer_raw_int;
write_pointer_extra_ts <= write_pointer_extra_ts_int;
rx_mem_free_int <= rx_mem_free_int_int;
----------------------------------------------------------------------------
-- Driving bus aliases
......@@ -196,7 +209,7 @@ begin
read_pointer_proc : process(clk_sys, res_n, drv_erase_rx)
begin
if (res_n = ACT_RESET or drv_erase_rx = '1') then
read_pointer <= 0;
read_pointer_int <= 0;
elsif (rising_edge(clk_sys)) then
......@@ -204,7 +217,7 @@ begin
-- Moving to next word by reading (if there is sth to read).
--------------------------------------------------------------------
if (read_increment = '1') then
read_pointer <= read_pointer_inc_1;
read_pointer_int <= read_pointer_inc_1_int;
end if;
end if;
......@@ -220,31 +233,31 @@ begin
write_pointer_proc : process(clk_sys, res_n, drv_erase_rx)
begin
if (res_n = ACT_RESET or drv_erase_rx = '1') then
write_pointer <= 0;
write_pointer_raw <= 0;
write_pointer_int <= 0;
write_pointer_raw_int <= 0;
elsif (rising_edge(clk_sys)) then
--------------------------------------------------------------------
-- Loading "write_pointer_raw" to "write_pointer" when frame is
-- Loading "write_pointer_raw_int" to "write_pointer_int" when frame is
-- committed.
--------------------------------------------------------------------
if (commit_rx_frame = '1') then
write_pointer <= write_pointer_raw;
write_pointer_int <= write_pointer_raw_int;
end if;
--------------------------------------------------------------------
-- Updating "write_pointer_raw":
-- Updating "write_pointer_raw_int":
-- 1. Increment when word is written to memory.
-- 2. Reset when "rec_abort" is active (Error frame) or
-- frame finished and overrun occurred meanwhile. Reset to
-- value of last commited write pointer.
--------------------------------------------------------------------
if (write_raw_OK = '1') then
write_pointer_raw <= (write_pointer_raw + 1) mod buff_size;
write_pointer_raw_int<= (write_pointer_raw_int + 1) mod buff_size;
elsif (rec_abort = '1' or commit_overrun_abort = '1') then
write_pointer_raw <= write_pointer;
write_pointer_raw_int <= write_pointer_int;
end if;
......@@ -258,7 +271,7 @@ begin
extra_write_ptr_proc : process(clk_sys, res_n, drv_erase_rx)
begin
if (res_n = ACT_RESET or drv_erase_rx = '1') then
write_pointer_extra_ts <= 0;
write_pointer_extra_ts_int <= 0;
elsif (rising_edge(clk_sys)) then
......@@ -269,10 +282,10 @@ begin
-- Second one is offset by 4.
--------------------------------------------------------------------
if (store_extra_wr_ptr = '1') then
write_pointer_extra_ts <= write_pointer;
write_pointer_extra_ts_int <= write_pointer_int;
elsif (inc_extra_wr_ptr = '1') then
write_pointer_extra_ts <= (write_pointer_extra_ts + 1) mod
write_pointer_extra_ts_int <= (write_pointer_extra_ts_int + 1) mod
buff_size;
end if;
......@@ -287,7 +300,7 @@ begin
mem_free_proc : process(clk_sys, res_n, drv_erase_rx)
begin
if (res_n = ACT_RESET or drv_erase_rx = '1') then
rx_mem_free_int <= buff_size;
rx_mem_free_int_int <= buff_size;
rx_mem_free_raw <= buff_size;
elsif (rising_edge(clk_sys)) then
......@@ -316,7 +329,7 @@ begin
-- Abort, or abort was previously flaged -> Revert last commited
-- value.
if (rec_abort = '1' or commit_overrun_abort = '1') then
rx_mem_free_raw <= rx_mem_free_int;
rx_mem_free_raw <= rx_mem_free_int_int;
-- No read, write only, decrement by 1.
elsif (write_raw_OK = '1') then
......@@ -331,13 +344,13 @@ begin
--------------------------------------------------------------------
if (read_increment = '1') then
if (commit_rx_frame = '1') then
rx_mem_free_int <= rx_mem_free_raw_inc_1;
rx_mem_free_int_int <= rx_mem_free_raw_inc_1;
else
rx_mem_free_int <= rx_mem_free_int_inc_1;
rx_mem_free_int_int <= rx_mem_free_int_inc_1;
end if;
elsif (commit_rx_frame = '1') then
rx_mem_free_int <= rx_mem_free_raw;
rx_mem_free_int_int <= rx_mem_free_raw;
end if;
end if;
......@@ -347,9 +360,9 @@ begin
----------------------------------------------------------------------------
-- Calculating incremented value of free memory combinationally
----------------------------------------------------------------------------
mem_free_arith_proc : process(rx_mem_free_int, rx_mem_free_raw)
mem_free_arith_proc : process(rx_mem_free_int_int, rx_mem_free_raw)
begin
rx_mem_free_int_inc_1 <= rx_mem_free_int + 1;
rx_mem_free_int_inc_1 <= rx_mem_free_int_int + 1;
rx_mem_free_raw_inc_1 <= rx_mem_free_raw + 1;
rx_mem_free_raw_dec_1 <= rx_mem_free_raw - 1;
end process;
......@@ -359,12 +372,12 @@ begin
-- for two things:
-- 1. Actual Increment of Read pointer during read of RX_DATA.
-- 2. Adressing RX Buffer RAM read side by incremented value to avoid one
-- clock cycle delay on "read_pointer" and thus allow bursts on read
-- clock cycle delay on "read_pointer_int" and thus allow bursts on read
-- from RX_DATA register!
----------------------------------------------------------------------------
read_pointer_inc_proc : process(read_pointer)
read_pointer_inc_proc : process(read_pointer_int)
begin
read_pointer_inc_1 <= (read_pointer + 1) mod buff_size;
read_pointer_inc_1_int <= (read_pointer_int + 1) mod buff_size;
end process;
end architecture;
......@@ -45,8 +45,8 @@ Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
use work.CANcomponents.ALL;
USE WORK.can_constants.ALL;
use work.can_components.ALL;
entity CAN_Wrapper is
......
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