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CTU CAN FD IP Core
Commit 4e854a0b authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Separated CRC circuits to a wrapper. Included CRC mux to this 

wrapper. Output is already selected CRC based on selector signal.
parent 1e206b2b
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Showing with 373 additions and 171 deletions
src/Libraries/CANcomponents.vhd
View file @ 4e854a0b
......@@ -786,6 +786,37 @@ package CANcomponents is
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CRC wrapper
----------------------------------------------------------------------------
component crc_wrapper is
generic(
constant crc15_pol : std_logic_vector(15 downto 0) := x"C599";
constant crc17_pol : std_logic_vector(19 downto 0) := x"3685B";
constant crc21_pol : std_logic_vector(23 downto 0) := x"302899"
);
port(
signal res_n :in std_logic;
signal clk_sys :in std_logic;
signal data_tx_nbs :in std_logic;
signal data_tx_wbs :in std_logic;
signal data_rx_wbs :in std_logic;
signal data_rx_nbs :in std_logic;
signal trig_tx_nbs :in std_logic;
signal trig_tx_wbs :in std_logic;
signal trig_rx_wbs :in std_logic;
signal trig_rx_nbs :in std_logic;
signal enable :in std_logic;
signal drv_bus :in std_logic_vector(1023 downto 0);
signal use_rx_crc :in std_logic;
signal use_wbs_crc :in std_logic;
signal crc15 :out std_logic_vector(14 downto 0);
signal crc17 :out std_logic_vector(16 downto 0);
signal crc21 :out std_logic_vector(20 downto 0)
);
end component;
----------------------------------------------------------------------------
-- CAN CRC module
----------------------------------------------------------------------------
......
src/can_core/can_core.vhd
View file @ 4e854a0b
......@@ -482,28 +482,9 @@ architecture rtl of can_core is
-- CRC Interfaces
-- Transition from 0 to 1 erases the CRC and operation holds as long
-- as enable=1
signal crc_enable : std_logic;
-- CRC calculated with bit Stuffing from RX Data
signal crc15_wbs_rx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_wbs_rx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_wbs_rx : std_logic_vector(20 downto 0); --CRC 21
-- CRC calculated without bit Stuffing from RX Data
signal crc15_nbs_rx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_nbs_rx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_nbs_rx : std_logic_vector(20 downto 0); --CRC 21
-- CRC calculated with bit Stuffing from TX Data
signal crc15_wbs_tx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_wbs_tx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_wbs_tx : std_logic_vector(20 downto 0); --CRC 21
-- CRC calculated without bit Stuffing from TX Data
signal crc15_nbs_tx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_nbs_tx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_nbs_tx : std_logic_vector(20 downto 0); --CRC 21
signal crc_enable : std_logic;
signal crc_mux_sel : std_logic_vector(1 downto 0);
-- Final CRC chosen based on the type of transcieved/recieved frame
signal crc15 : std_logic_vector(14 downto 0); --CRC 15
......@@ -540,17 +521,8 @@ architecture rtl of can_core is
for fault_confinement_comp : fault_confinement
use entity work.fault_confinement(rtl);
for crc_wbs_rx_comp : can_crc
use entity work.can_crc(rtl);
for crc_nbs_rx_comp : can_crc
use entity work.can_crc(rtl);
for crc_wbs_tx_comp : can_crc
use entity work.can_crc(rtl);
for crc_nbs_tx_comp : can_crc
use entity work.can_crc(rtl);
for crc_wrapper_comp : crc_wrapper
use entity work.crc_wrapper(rtl);
for bit_stuffing_comp : bit_stuffing
use entity work.bit_stuffing(rtl);
......@@ -758,95 +730,40 @@ begin
----------------------------------------------------------------------------
-- CRC with bit stuffing from RX Data
----------------------------------------------------------------------------
crc_wbs_rx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
crc21_pol => CRC21_POL
)
port map(
data_in => data_crc_wbs,
clk_sys => clk_sys,
trig => crc_wbs_trig,
res_n => res_n,
enable => crc_enable,
drv_bus => drv_bus,
crc15 => crc15_wbs_rx,
crc17 => crc17_wbs_rx,
crc21 => crc21_wbs_rx
);
----------------------------------------------------------------------------
-- CRC no bit stuffing from RX Data
-- CRC wrapper component. Contains 4 CRC circuits and CRC mux.
----------------------------------------------------------------------------
crc_nbs_rx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
crc21_pol => CRC21_POL
)
port map(
data_in => data_crc_nbs,
clk_sys => clk_sys,
trig => crc_nbs_trig,
res_n => res_n,
enable => crc_enable,
drv_bus => drv_bus,
crc15 => crc15_nbs_rx,
crc17 => crc17_nbs_rx,
crc21 => crc21_nbs_rx
);
----------------------------------------------------------------------------
-- CRC with bit stuffing from TX Data
----------------------------------------------------------------------------
crc_wbs_tx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
crc21_pol => CRC21_POL
)
port map(
data_in => data_tx_int,
clk_sys => clk_sys,
trig => crc_tx_wbs_trig,
res_n => res_n,
enable => crc_enable,
drv_bus => drv_bus,
crc15 => crc15_wbs_tx,
crc17 => crc17_wbs_tx,
crc21 => crc21_wbs_tx
);
crc_wrapper_comp : crc_wrapper
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
crc21_pol => CRC21_POL
)
port map(
res_n => res_n,
clk_sys => clk_sys,
----------------------------------------------------------------------------
-- CRC no bit stuffing from TX Data
----------------------------------------------------------------------------
crc_nbs_tx_comp : can_crc
generic map(
crc15_pol => CRC15_POL,
crc17_pol => CRC17_POL,
crc21_pol => CRC21_POL
)
port map(
data_in => data_tx_before_stuff,
clk_sys => clk_sys,
-- TX no bit stuffing crc is calculated with the same
-- trigger as bit stuffing
trig => tran_trig_del_1,
res_n => res_n,
enable => crc_enable,
drv_bus => drv_bus,
crc15 => crc15_nbs_tx,
crc17 => crc17_nbs_tx,
crc21 => crc21_nbs_tx
);
-- Data inputs
data_tx_nbs => data_tx_before_stuff,
data_tx_wbs => data_tx_int,
data_rx_wbs => data_crc_wbs,
data_rx_nbs => data_crc_nbs,
-- Trigger signals
trig_tx_nbs => tran_trig_del_1,
trig_tx_wbs => crc_tx_wbs_trig,
trig_rx_wbs => crc_wbs_trig,
trig_rx_nbs => crc_nbs_trig,
-- Control signals
enable => crc_enable,
drv_bus => drv_bus,
use_rx_crc => crc_mux_sel(0),
use_wbs_crc => crc_mux_sel(1),
crc15 => crc15,
crc17 => crc17,
crc21 => crc21
);
----------------------------------------------------------------------------
......@@ -921,58 +838,22 @@ begin
ssp_reset <= ssp_reset_int;
trv_delay_calib <= trv_delay_calib_int;
---------------------------------------------------------------------------
-- CRC Multiplexor selector:
-- bit 0 : 1 - use rx CRC, 0 - use tx CRC
-- bit 1 : 1 - use wbs crc, 0 - use nbs CRC
---------------------------------------------------------------------------
crc_mux_sel <= "10" when (OP_State = transciever and tran_frame_type = FD_CAN)
else
"00" when (OP_State = transciever and tran_frame_type = NORMAL_CAN)
else
"11" when (OP_State = reciever and rec_frame_type = FD_CAN)
else
"01" when (OP_State = reciever and rec_frame_type = NORMAL_CAN)
else
"00";
----------------------------------------------------------------------------
-- CRC Multiplexors.
--
-- CRC data sources like so:
-- 1. Transceiver, CAN FD Frame -> TX Data after bit stuffing.
-- 2. Transceiver, CAN 2.0 Frame -> TX Data before bit stuffing.
-- 3. Receiver, CAN FD Frame -> RX Data before bit destuffing.
-- 4. Receiver, CAN 2.0 Frame -> RX Data after bit destuffing.
----------------------------------------------------------------------------
crc15 <= crc15_wbs_tx when (OP_State = transciever and
tran_frame_type = FD_CAN) else
crc15_nbs_tx when (OP_State = transciever and
tran_frame_type = NORMAL_CAN) else
crc15_wbs_rx when (OP_State = reciever and
rec_frame_type = FD_CAN) else
crc15_nbs_rx when (OP_State = reciever and
rec_frame_type = NORMAL_CAN) else
"000000000000000";
crc17 <= crc17_wbs_tx when (OP_State = transciever and
tran_frame_type = FD_CAN) else
crc17_nbs_tx when (OP_State = transciever and
tran_frame_type = NORMAL_CAN) else
crc17_wbs_rx when (OP_State = reciever and
rec_frame_type = FD_CAN) else
crc17_nbs_rx when (OP_State = reciever and
rec_frame_type = NORMAL_CAN) else
"00000000000000000";
crc21 <= crc21_wbs_tx when (OP_State = transciever and
tran_frame_type = FD_CAN) else
crc21_nbs_tx when (OP_State = transciever and
tran_frame_type = NORMAL_CAN) else
crc21_wbs_rx when (OP_State = reciever and
rec_frame_type = FD_CAN) else
crc21_nbs_rx when (OP_State = reciever and
rec_frame_type = NORMAL_CAN) else
"000000000000000000000";
----------------------------------------------------------------------------
-- Multiplexing of stuff counter and destuff counter
......
src/can_core/crc/crc_wrapper.vhd 0 → 100644
View file @ 4e854a0b
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- CRC Wrapper for CTU CAN FD. Contains 4 CRC circuits. Following CRCs are
-- calculated:
-- 1. From TX data before bit-stuffing (tx_nbs)
-- 2. From TX data after bit-stuffing (tx_wbs)
-- 3. From RX data before bit-destuffing (rx_wbs)
-- 4. From RX data after bit-destuffing (rx_nbs)
--
-- CRCs are multiplexed combinationally to output of wrapper via signals:
-- use_rx_crc, use_wbs_crc.
-- 4 combinations on these signals choose the final CRC.
--------------------------------------------------------------------------------
-- Revision History:
-- 28.12.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
use work.CANconstants.all;
use work.CAN_FD_register_map.all;
use work.CANcomponents.all;
entity crc_wrapper is
generic(
constant crc15_pol : std_logic_vector(15 downto 0) := x"C599";
constant crc17_pol : std_logic_vector(19 downto 0) := x"3685B";
constant crc21_pol : std_logic_vector(23 downto 0) := x"302899"
);
port(
------------------------------------------------------------------------
-- Reset and clock
------------------------------------------------------------------------
signal res_n :in std_logic;
signal clk_sys :in std_logic;
------------------------------------------------------------------------
-- Serial data inputs
------------------------------------------------------------------------
signal data_tx_nbs :in std_logic;
signal data_tx_wbs :in std_logic;
signal data_rx_wbs :in std_logic;
signal data_rx_nbs :in std_logic;
------------------------------------------------------------------------
-- Trigger signals to process the data on each CRC input.
------------------------------------------------------------------------
signal trig_tx_nbs :in std_logic;
signal trig_tx_wbs :in std_logic;
signal trig_rx_wbs :in std_logic;
signal trig_rx_nbs :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- Enable for all CRC circuits.
signal enable :in std_logic;
-- Driving bus
signal drv_bus :in std_logic_vector(1023 downto 0);
-- When '1' CRCs from RX path will be chosen, otherwise TX
signal use_rx_crc :in std_logic;
-- When '1' CRCs with bit stuffing will be chosen, otherwise no bit
-- stuffing!
signal use_wbs_crc :in std_logic;
------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------
signal crc15 :out std_logic_vector(14 downto 0);
signal crc17 :out std_logic_vector(16 downto 0);
signal crc21 :out std_logic_vector(20 downto 0)
);
end entity;
architecture rtl of crc_wrapper is
---------------------------------------------------------------------------
-- Immediate outputs of CRC circuits
---------------------------------------------------------------------------
-- CRC calculated with bit Stuffing from RX Data
signal crc15_wbs_rx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_wbs_rx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_wbs_rx : std_logic_vector(20 downto 0); --CRC 21
-- CRC calculated without bit Stuffing from RX Data
signal crc15_nbs_rx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_nbs_rx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_nbs_rx : std_logic_vector(20 downto 0); --CRC 21
-- CRC calculated with bit Stuffing from TX Data
signal crc15_wbs_tx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_wbs_tx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_wbs_tx : std_logic_vector(20 downto 0); --CRC 21
-- CRC calculated without bit Stuffing from TX Data
signal crc15_nbs_tx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_nbs_tx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_nbs_tx : std_logic_vector(20 downto 0); --CRC 21
---------------------------------------------------------------------------
-- Intermediate results of first level muxes (after decision between
-- WBS and NBS)
---------------------------------------------------------------------------
signal crc15_tx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_tx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_tx : std_logic_vector(20 downto 0); --CRC 21
signal crc15_rx : std_logic_vector(14 downto 0); --CRC 15
signal crc17_rx : std_logic_vector(16 downto 0); --CRC 17
signal crc21_rx : std_logic_vector(20 downto 0); --CRC 21
begin
----------------------------------------------------------------------------
-- CRC with bit stuffing from RX Data
----------------------------------------------------------------------------
crc_wbs_rx_comp : can_crc
generic map(
crc15_pol => crc15_pol,
crc17_pol => crc17_pol,
crc21_pol => crc21_pol
)
port map(
data_in => data_rx_wbs,
clk_sys => clk_sys,
trig => trig_rx_wbs,
res_n => res_n,
enable => enable,
drv_bus => drv_bus,
crc15 => crc15_wbs_rx,
crc17 => crc17_wbs_rx,
crc21 => crc21_wbs_rx
);
----------------------------------------------------------------------------
-- CRC no bit stuffing from RX Data
----------------------------------------------------------------------------
crc_nbs_rx_comp : can_crc
generic map(
crc15_pol => crc15_pol,
crc17_pol => crc17_pol,
crc21_pol => crc21_pol
)
port map(
data_in => data_rx_nbs,
clk_sys => clk_sys,
trig => trig_rx_nbs,
res_n => res_n,
enable => enable,
drv_bus => drv_bus,
crc15 => crc15_nbs_rx,
crc17 => crc17_nbs_rx,
crc21 => crc21_nbs_rx
);
----------------------------------------------------------------------------
-- CRC with bit stuffing from TX Data
----------------------------------------------------------------------------
crc_wbs_tx_comp : can_crc
generic map(
crc15_pol => crc15_pol,
crc17_pol => crc17_pol,
crc21_pol => crc21_pol
)
port map(
data_in => data_tx_wbs,
clk_sys => clk_sys,
trig => trig_tx_wbs,
res_n => res_n,
enable => enable,
drv_bus => drv_bus,
crc15 => crc15_wbs_tx,
crc17 => crc17_wbs_tx,
crc21 => crc21_wbs_tx
);
----------------------------------------------------------------------------
-- CRC no bit stuffing from TX Data
----------------------------------------------------------------------------
crc_nbs_tx_comp : can_crc
generic map(
crc15_pol => crc15_pol,
crc17_pol => crc17_pol,
crc21_pol => crc21_pol
)
port map(
data_in => data_tx_nbs,
clk_sys => clk_sys,
trig => trig_tx_nbs,
res_n => res_n,
enable => enable,
drv_bus => drv_bus,
crc15 => crc15_nbs_tx,
crc17 => crc17_nbs_tx,
crc21 => crc21_nbs_tx
);
----------------------------------------------------------------------------
-- First stage muxes. Selecting between WBS and NBS CRCs on both TX and
-- RX datapaths.
----------------------------------------------------------------------------
-- RX
crc15_rx <= crc15_wbs_rx when (use_wbs_crc = '1') else
crc15_nbs_rx;
crc17_rx <= crc17_wbs_rx when (use_wbs_crc = '1') else
crc17_nbs_rx;
crc21_rx <= crc21_wbs_rx when (use_wbs_crc = '1') else
crc21_nbs_rx;
-- TX
crc15_tx <= crc15_wbs_tx when (use_wbs_crc = '1') else
crc15_nbs_tx;
crc17_tx <= crc17_wbs_tx when (use_wbs_crc = '1') else
crc17_nbs_tx;
crc21_tx <= crc21_wbs_tx when (use_wbs_crc = '1') else
crc21_nbs_tx;
----------------------------------------------------------------------------
-- Second stage muxes. Selecting between RX and TX CRCs.
----------------------------------------------------------------------------
crc15 <= crc15_rx when (use_rx_crc = '1') else
crc15_tx;
crc17 <= crc17_rx when (use_rx_crc = '1') else
crc17_tx;
crc21 <= crc21_rx when (use_rx_crc = '1') else
crc21_tx;
end architecture;
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