Added sources for generated register map.

Set reg.map files to VHDL 2008 due to usage of data_width generic in the same interface list.

Added sources for generated register map.
Set reg.map files to VHDL 2008 due to usage of data_width generic in the same interface list.
4d946d7e · Ille, Ondrej, Ing. · eadf0eff · 4d946d7e
Commit 4d946d7e authored Dec 08, 2018 by Ille, Ondrej, Ing.
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synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr +469 -20

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