Commit 4d4468c1 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added coverage of Timestamp options. Added Data overrun

coverage.
parent 448b4303
......@@ -117,8 +117,9 @@ architecture rx_buf_unit_test of CAN_test is
-- Driving bus aliases
signal drv_rtsopt : std_logic := RTS_END;
signal drv_read_start : std_logic := '0';
signal drv_clr_ovr : std_logic := '0';
----------------------------------------------------------------------------
-- Test specific signals
----------------------------------------------------------------------------
......@@ -138,6 +139,9 @@ architecture rx_buf_unit_test of CAN_test is
signal exit_imm_d_2 : boolean := false;
signal exit_imm_d_3 : boolean := false;
-- Additional random counter
signal rand_ctr_3 : natural range 0 to RAND_POOL_SIZE := 0;
----------------------------------------------------------------------------
-- Memory declarations for memories where data are read out
----------------------------------------------------------------------------
......@@ -216,7 +220,7 @@ architecture rx_buf_unit_test of CAN_test is
wait for 0 ns;
end loop;
end if;
-- At the end we need to move one more time
-- in_pointer <= in_pointer+1;
wait for 0 ns;
......@@ -284,6 +288,7 @@ architecture rx_buf_unit_test of CAN_test is
signal rec_message_valid :out std_logic;
signal drv_rtsopt :in std_logic;
signal drv_clr_ovr :inout std_logic;
signal memory :inout eval_mem_test;
signal in_pointer :inout natural;
......@@ -293,14 +298,34 @@ architecture rx_buf_unit_test of CAN_test is
variable CAN_frame : SW_CAN_frame_type;
variable stored_ts : std_logic_vector(63 downto 0);
variable rand_val : natural;
variable abort_present : boolean;
variable abort_present : boolean := false;
variable id_out : std_logic_vector(28 downto 0);
begin
CAN_generate_frame(rand_ctr, CAN_frame);
stored_ts := (OTHERS => '0');
------------------------------------------------------------------------
-- Initiate frame storing by clearing possible overrun from before.
-- It might have happened that Overrun was generated at the same time
-- as there was intent abort. In that case, the frame was aborted,
-- overrun was not cleared and stayed till next frame. Storing of
-- next frame then evaluated overrun as present and did not store the
-- frame to input memory!
------------------------------------------------------------------------
drv_clr_ovr <= '1';
wait until rising_edge(clk_sys);
drv_clr_ovr <= '0';
wait for 1 ns;
-- Check that overrun was cleared
if (rx_data_overrun = '1') then
log("Overrun not cleared!", error_l, log_level);
end if;
------------------------------------------------------------------------
-- Initiate Frame by SOF pulse and store timestamp!
------------------------------------------------------------------------
sof_pulse <= '1';
if (drv_rtsopt = RTS_BEG) then
stored_ts := std_logic_vector(to_unsigned(
......@@ -310,16 +335,20 @@ architecture rx_buf_unit_test of CAN_test is
sof_pulse <= '0';
wait until rising_edge(clk_sys);
------------------------------------------------------------------------
-- Wait Random time (to emulate CAN ID). No real need to emulate real
-- length of Identifier! Emulate random error also during this time,
-- error frame may come also before any storing started and can not FUCK
-- UP the buffer.
------------------------------------------------------------------------
wait_rand_cycles(rand_ctr, clk_sys, 10, 50);
generate_random_abort(rand_ctr, rec_abort, clk_sys, abort_present, 0.1,
log_level);
if (abort_present) then
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
return;
end if;
......@@ -334,6 +363,7 @@ architecture rx_buf_unit_test of CAN_test is
rec_brs <= CAN_frame.brs;
rec_esi <= CAN_frame.esi;
rec_rtr <= CAN_frame.rtr;
log("Storing metadata", info_l, log_level);
wait until rising_edge(clk_sys);
......@@ -343,13 +373,15 @@ architecture rx_buf_unit_test of CAN_test is
store_metadata <= '0';
wait until rising_edge(clk_sys);
------------------------------------------------------------------------
-- Store data words
------------------------------------------------------------------------
if (CAN_frame.data_length > 0) then
for i in 0 to ((CAN_frame.data_length - 1) / 4) loop
-- Wait random time between store of individual data bytes!
wait_rand_cycles(rand_ctr, clk_sys, 10, 50);
-- Send signal to store data
store_data_word <= CAN_frame.data((i * 4) + 3) &
CAN_frame.data((i * 4) + 2) &
......@@ -365,6 +397,8 @@ architecture rx_buf_unit_test of CAN_test is
generate_random_abort(rand_ctr, rec_abort, clk_sys, abort_present,
0.05, log_level);
if (abort_present) then
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
return;
end if;
end loop;
......@@ -372,14 +406,18 @@ architecture rx_buf_unit_test of CAN_test is
wait_rand_cycles(rand_ctr, clk_sys, 30, 100);
------------------------------------------------------------------------
-- If we got here, no abort was generated, thus frame was stored OK!
-- We commit frame to the buffer and store it to test memories!
------------------------------------------------------------------------
rec_message_valid <= '1';
log("Frame valid!", info_l, log_level);
wait until rising_edge(clk_sys);
------------------------------------------------------------------------
-- Timestamp must be marked, if we are interested in END OF Frame
-- Timestamp!
------------------------------------------------------------------------
if (drv_rtsopt = RTS_END) then
CAN_frame.timestamp := timestamp;
else
......@@ -387,10 +425,23 @@ architecture rx_buf_unit_test of CAN_test is
end if;
rec_message_valid <= '0';
------------------------------------------------------------------------
-- Check that during whole storing of this frame data overrun did not
-- occur!
------------------------------------------------------------------------
if (rx_data_overrun = '1') then
log("Data overrun appeared!", info_l, log_level);
------------------------------------------------------------------------
-- If overrun did not happend, insert frame to input test memory!
------------------------------------------------------------------------
else
insert_frame_test_mem(CAN_frame, memory, in_pointer);
end if;
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
wait until rising_edge(clk_sys);
insert_frame_test_mem(CAN_frame, memory, in_pointer);
end procedure;
......@@ -404,6 +455,7 @@ architecture rx_buf_unit_test of CAN_test is
signal drv_read_start :inout std_logic;
signal clk_sys :in std_logic;
signal out_mem :out eval_mem_test;
signal in_mem :in eval_mem_test;
signal out_pointer :inout natural
)is
variable rwcnt : natural;
......@@ -417,6 +469,14 @@ architecture rx_buf_unit_test of CAN_test is
for i in 0 to rwcnt loop
drv_read_start <= '1';
out_mem(out_pointer) <= buff_out;
-- Check that word is exactly matching the word in in_mem at the
-- same position
if (buff_out /= in_mem(out_pointer)) then
log("Buffer FUCKED UP, inex: " & integer'image(out_pointer),
error_l, log_level);
end if;
out_pointer <= out_pointer + 1;
wait until rising_edge(clk_sys);
drv_read_start <= '0';
......@@ -509,7 +569,8 @@ begin
false;
drv_bus(DRV_READ_START_INDEX) <= drv_read_start;
drv_bus(DRV_RTSOPT_INDEX) <= drv_rtsopt;
drv_bus(DRV_RTSOPT_INDEX) <= drv_rtsopt;
drv_bus(DRV_CLR_OVR_INDEX) <= drv_clr_ovr;
----------------------------------------------------------------------------
......@@ -556,8 +617,7 @@ begin
rec_dlc_in, rec_frame_type_in, rec_ident_type_in, rec_brs,
rec_esi, rec_is_rtr, sof_pulse, store_metadata, store_data,
store_data_word, rec_abort, rec_message_valid, drv_rtsopt,
in_mem, in_pointer, timestamp, log_level);
drv_clr_ovr, in_mem, in_pointer, timestamp, log_level);
end loop;
-- Now input memory is full
......@@ -591,12 +651,16 @@ begin
wait for 5 ns;
end if;
------------------------------------------------------------------------
-- Read frames as long as Output memory is not filled. Wait random time
-- in between, to allow for data overrun to occur!
------------------------------------------------------------------------
while (out_mem_full = false) loop
if (rx_empty = '0') then
read_frame(rx_read_buff, drv_read_start, clk_sys, out_mem,
out_pointer);
read_frame(rx_read_buff, drv_read_start, clk_sys, out_mem,
in_mem, out_pointer);
wait_rand_cycles(rand_ctr_3, clk_sys, 200, 250);
end if;
wait until rising_edge(clk_sys);
end loop;
......@@ -625,15 +689,11 @@ begin
iteration_done <= false;
-- Wait until data we inserted from the buffer and model
wait until in_mem_full = true;
-- Wait until data are read!
wait until rx_message_count = "00000000000";
-- Wait until data we inserted into input memory and read back by
-- data reader.
wait until (in_mem_full = true) and (out_mem_full = true);
-- Now that all the data wer inserted into the buffer we will wait until
-- it it for sure read back OK. That means buffer_size*2 clock cycles!
wait for buff_size * 2 * clk_time;
wait for 3000 ns;
-- Now compare the data
cons_res := false;
......
......@@ -83,6 +83,7 @@ add wave -label "Free 32bit words" -unsigned $TCOMP/rx_mem_free
add wave -label "Read pointer" -unsigned $TCOMP/rx_read_pointer_pos
add wave -label "Write pointer" -unsigned $TCOMP/rx_write_pointer_pos
add wave -label "Output word" -hexadecimal $TCOMP/rx_read_buff
add wave -label "Data overrun" -hexadecimal $TCOMP/rx_data_overrun
add wave -noupdate -divider -height 20 "RX Buffer internal signals"
add wave -label "RX Buffer FSM" -hexadecimal $TCOMP/rx_Buffer_comp/rx_fsm
......@@ -99,7 +100,6 @@ add wave -label "Memory write pointer" -hexadecimal $TCOMP/rx_Buffer_comp/memory
add wave -label "Captured timestamp" -hexadecimal $TCOMP/rx_Buffer_comp/timestamp_capture
add wave -label "Commit RX Frame" -hexadecimal $TCOMP/rx_Buffer_comp/commit_rx_frame
add wave -label "Data overrun internal" -hexadecimal $TCOMP/rx_Buffer_comp/data_overrun_int
add wave -label "Mem free raw" $TCOMP/rx_Buffer_comp/rx_mem_free_raw
add wave -noupdate -divider -height 20 "Testbench internal signals"
......
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