Commit 4b68c064 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

doc: Fix datasheet link

parent 8da74a77
...@@ -22,7 +22,7 @@ Architecture of CTU CAN FD is described in: ...@@ -22,7 +22,7 @@ Architecture of CTU CAN FD is described in:
[![System architecture](https://img.shields.io/badge/System_architecture--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ctu_can_fd_architecture.pdf) [![System architecture](https://img.shields.io/badge/System_architecture--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ctu_can_fd_architecture.pdf)
Functional description of CTU CAN FD is in datasheet: Functional description of CTU CAN FD is in datasheet:
[![Datasheet](https://img.shields.io/badge/Datasheet--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ProgDokum.pdf) [![Datasheet](https://img.shields.io/badge/Datasheet--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf)
CTU CAN FD is written with frequent usage of clock enables (FPGA) allowing inferred clock gating. CTU CAN FD is written with frequent usage of clock enables (FPGA) allowing inferred clock gating.
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment