Commit 4b68c064 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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doc: Fix datasheet link

parent 8da74a77
......@@ -22,7 +22,7 @@ Architecture of CTU CAN FD is described in:
[![System architecture](](
Functional description of CTU CAN FD is in datasheet:
CTU CAN FD is written with frequent usage of clock enables (FPGA) allowing inferred clock gating.
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