Commit 487484cd authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Move bit error detection to a separate module.

parent 5d48a71e
Pipeline #6542 failed with stage
in 35 seconds
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Detects bit error.
--------------------------------------------------------------------------------
-- 28.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity bit_errror_detector is
generic(
-- Reset polarity
constant reset_polarity : std_logic
);
port(
------------------------------------------------------------------------
-- Clock and Async reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- Bit error detection enabled
signal bit_err_enable :in std_logic;
-- Core is enabled
signal drv_ena :in std_logic;
-- Sample control (nominal, data, secondary)
signal sp_control :in std_logic_vector(1 downto 0);
-- Input sample signals
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
-----------------------------------------------------------------------
-- TX Data inputs
-----------------------------------------------------------------------
-- Regulary transmitted data
signal data_tx :in std_logic;
-- Delayed transmitted data (for detection in secondary sampling point)
signal data_tx_delayed :in std_logic;
-----------------------------------------------------------------------
-- RX Data inputs
-----------------------------------------------------------------------
-- Receieved data in Nominal Bit time (either directly sampled data,
-- or tripple sampling output)
signal data_rx_nbt :in std_logic;
-- Received data (Nominal and Data)
signal can_rx_i :in std_logic;
------------------------------------------------------------------------
-- Bit error output
------------------------------------------------------------------------
signal bit_error : out std_logic
);
end entity;
architecture rtl of bit_errror_detector is
-- Internal sample signal (muxed for NBT, DBT and SAMPLE)
signal sample : std_logic;
-- Expected bit value (TX, from SYNC)
signal exp_data : std_logic;
-- Actual data value (RX, from Sample point)
signal act_data : std_logic;
-- Bit error detected value
signal bit_error_d : std_logic;
signal bit_error_q : std_logic;
begin
----------------------------------------------------------------------------
-- Sample point multiplexor
----------------------------------------------------------------------------
sample <= sample_nbt when (sp_control = NOMINAL_SAMPLE) else
sample_dbt when (sp_control = DATA_SAMPLE) else
sample_sec when (sp_control = SECONDARY_SAMPLE) else
'0';
----------------------------------------------------------------------------
-- Expected data mux. Choose between TX data and delayed TX Data
----------------------------------------------------------------------------
exp_data <= data_tx_delayed when (sp_control = SECONDARY_SAMPLE) else
data_tx;
----------------------------------------------------------------------------
-- Actual data. Consider tripple sampling for Nominal Bit-rate
----------------------------------------------------------------------------
act_data <= data_rx_nbt when (sp_control = NOMINAL_SAMPLE) else
can_rx_i;
----------------------------------------------------------------------------
-- Bit Error detection. If expected data is not equal to actual data in
-- sample point -> Bit Error!
----------------------------------------------------------------------------
bit_error_d <= '0' when (drv_ena = CTU_CAN_DISABLED or bit_err_enable = '0') else
'1' when (exp_data /= act_data and sample = '1') else
'0' when (exp_data = act_data and sample = '1') else
bit_error_q;
----------------------------------------------------------------------------
-- Bit error register
----------------------------------------------------------------------------
bit_error_reg_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
bit_error_q <= '0';
elsif (rising_edge(clk_sys)) then
bit_error_q <= bit_error_d;
end if;
end process;
-- Propagation to output
bit_error <= bit_error_q;
end architecture;
\ No newline at end of file
......@@ -117,7 +117,10 @@ entity bus_sampling is
-- Turn off only when Synthetizer puts synchronisation chain automati-
-- cally on the output pins! Otherwise metastability issues will occur!
------------------------------------------------------------------------
constant use_Sync : boolean := false
constant use_Sync : boolean := false;
-- Reset polarity
constant reset_polarity : std_logic := '0'
);
PORT(
------------------------------------------------------------------------
......@@ -266,7 +269,7 @@ architecture rtl of bus_sampling is
-- Delayed TX Data from TX Data shift register at position of secondary
-- sampling point.
signal tx_data_delayed : std_logic;
signal data_tx_delayed : std_logic;
-- Shift Register for generating secondary sampling signal
signal sample_sec_shift : std_logic_vector
......@@ -466,7 +469,7 @@ begin
write => sample_dbt,
read => sample_sec,
data_in => data_tx,
data_out => tx_data_delayed
data_out => data_tx_delayed
);
......@@ -537,6 +540,28 @@ begin
data_rx_nbt <= CAN_rx_trs_majority when (drv_sam = TSM_ENABLE) else
CAN_rx_i;
---------------------------------------------------------------------------
-- Bit error detector
---------------------------------------------------------------------------
bit_errror_detector_comp : bit_errror_detector
generic map(
reset_polarity => reset_polarity
)
port map(
clk_sys => clk_sys,
res_n => res_n,
bit_err_enable => bit_err_enable,
drv_ena => drv_ena,
sp_control => sp_control,
sample_nbt => sample_nbt,
sample_dbt => sample_dbt,
sample_sec => sample_sec,
data_tx => data_tx,
data_tx_delayed => data_tx_delayed,
data_rx_nbt => data_rx_nbt,
can_rx_i => can_rx_i,
bit_error => bit_Error_reg
);
----------------------------------------------------------------------------
-- Sampling of bus value
......@@ -588,80 +613,6 @@ begin
end if;
end process sample_proc;
----------------------------------------------------------------------------
-- Bit Error detection process
----------------------------------------------------------------------------
bit_err_detect_proc : process(res_n, clk_sys)
begin
if (res_n = ACT_RESET) then
bit_Error_reg <= '0';
elsif rising_edge(clk_sys) then
if (drv_ena = CTU_CAN_ENABLED and bit_err_enable = '1') then
case sp_control is
----------------------------------------------------------------
-- Sampling with nominal bit time
-- (normal CAN, transciever, reciever)
----------------------------------------------------------------
when NOMINAL_SAMPLE =>
if (sample_nbt = '1') then
-- If TX data are equal to RX Data -> No problem.
if (data_rx_nbt = data_tx) then
bit_Error_reg <= '0';
else
bit_Error_reg <= '1';
end if;
end if;
----------------------------------------------------------------
-- Sampling with data bit time (CAN FD, reciever)
----------------------------------------------------------------
when DATA_SAMPLE =>
if (sample_dbt = '1') then
--Bit Error detection when sampling
if (CAN_rx_i = data_tx) then
bit_Error_reg <= '0';
else
bit_Error_reg <= '1';
end if;
end if;
----------------------------------------------------------------
-- Sampling with transciever delay compensation
-- (CAN FD, transciever)
----------------------------------------------------------------
when SECONDARY_SAMPLE =>
if (sample_sec = '1') then
-- Bit Error comparison differs in this case, not actual
-- transmitted bit is compared, but delayed bit is
-- compared (in ssp_shift register)
if (CAN_rx_i = tx_data_delayed) then
bit_Error_reg <= '0';
else
bit_Error_reg <= '1';
end if;
end if;
when others =>
end case;
-- If whole Core is disabled, or Bit Error detection is disabled,
-- hold permanently in zero!
else
bit_Error_reg <= '0';
end if;
end if;
end process bit_err_detect_proc;
-- Propagating sampled data to CAN Core
data_rx <= prev_Sample;
......
......@@ -804,7 +804,8 @@ begin
bus_sampling_comp : bus_sampling
generic map (
use_Sync => use_sync
use_Sync => use_sync,
reset_polarity => ACT_RESET
)
port map(
clk_sys => clk_sys,
......
......@@ -729,7 +729,8 @@ package can_components is
----------------------------------------------------------------------------
component bus_sampling is
generic (
use_Sync : boolean
use_Sync : boolean;
reset_polarity : std_logic
);
port(
signal clk_sys : in std_logic;
......@@ -843,6 +844,27 @@ package can_components is
signal log_state_out : out logger_state_type
);
end component;
component bit_errror_detector is
generic(
constant reset_polarity : std_logic
);
port(
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal bit_err_enable :in std_logic;
signal drv_ena :in std_logic;
signal sp_control :in std_logic_vector(1 downto 0);
signal sample_nbt :in std_logic;
signal sample_dbt :in std_logic;
signal sample_sec :in std_logic;
signal data_tx :in std_logic;
signal data_tx_delayed :in std_logic;
signal data_rx_nbt :in std_logic;
signal can_rx_i :in std_logic;
signal bit_error :out std_logic
);
end component;
----------------------------------------------------------------------------
......
......@@ -151,7 +151,8 @@ begin
bus_sampling_comp : bus_sampling
GENERIC map(
use_Sync => true
use_Sync => true,
reset_polarity => '0'
)
PORT map(
clk_sys => clk_sys,
......
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