Commit 466e9a5a authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Merge branch '179-feature-test-clock-tolerance' into 'master'

Resolve "Feature test clock tolerance"

Closes #179

See merge request illeondr/CAN_FD_IP_Core!138
parents 1baf1a7b 352efe47
......@@ -217,8 +217,8 @@ begin
---------------------------------
-- Clock & timestamp generation
---------------------------------
clk_gen_proc: clock_gen_proc(period => f100_Mhz, duty => 50, epsilon_ppm => 0,
out_clk => p(i).clk_sys);
clk_gen_proc: clock_gen_proc(period => f100_Mhz, duty => 50,
epsilon_ppm => (i - 1) * 100, out_clk => p(i).clk_sys);
tsgen_proc: timestamp_gen_proc(p(i).clk_sys, p(i).timestamp);
end generate;
......
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