Commit 44af491e authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added TXT Buffer priority and Status to the register map.

parent 06674422
......@@ -1665,7 +1665,13 @@ hyperref[TRV_DELAY]{TRV\backslash textunderscore DELAY}\end_layout
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[TX_STATUS]{TX\backslash textunderscore STATUS}\end_layout
\end_inset
\end_layout
\end_inset
</cell>
......@@ -1673,7 +1679,13 @@ Reserved\end_layout
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[TX_STATUS]{TX\backslash textunderscore STATUS}\end_layout
\end_inset
\end_layout
\end_inset
</cell>
......@@ -1681,11 +1693,17 @@ Reserved\end_layout
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[TX_STATUS]{TX\backslash textunderscore STATUS}\end_layout
\end_inset
\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
......@@ -1713,7 +1731,13 @@ hyperref[TX_STATUS]{TX\backslash textunderscore STATUS}\end_layout
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[TX_SETTINGS]{TX\backslash textunderscore SETTINGS}\end_layout
\end_inset
\end_layout
\end_inset
</cell>
......@@ -1721,7 +1745,13 @@ Reserved\end_layout
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[TX_SETTINGS]{TX\backslash textunderscore SETTINGS}\end_layout
\end_inset
\end_layout
\end_inset
</cell>
......@@ -1729,11 +1759,17 @@ Reserved\end_layout
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
hyperref[TX_SETTINGS]{TX\backslash textunderscore SETTINGS}\end_layout
\end_inset
\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
......@@ -24456,10 +24492,10 @@ Type: read-only
Address: 0x58
\end_layout
\begin_layout Description
Size: 1 byte
Size: 4 bytes
\end_layout
\begin_layout Standard
Status of the TXT Buffers.
Status of TXT Buffers.
\end_layout
\begin_layout Standard
\noindent
......@@ -24489,7 +24525,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
7\end_layout
31\end_layout
\end_inset
</cell>
......@@ -24497,7 +24533,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
6\end_layout
30\end_layout
\end_inset
</cell>
......@@ -24505,7 +24541,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
5\end_layout
29\end_layout
\end_inset
</cell>
......@@ -24513,7 +24549,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
4\end_layout
28\end_layout
\end_inset
</cell>
......@@ -24521,7 +24557,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
3\end_layout
27\end_layout
\end_inset
</cell>
......@@ -24529,7 +24565,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
2\end_layout
26\end_layout
\end_inset
</cell>
......@@ -24537,7 +24573,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
1\end_layout
25\end_layout
\end_inset
</cell>
......@@ -24545,7 +24581,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
0\end_layout
24\end_layout
\end_inset
</cell>
......@@ -24559,7 +24595,7 @@ Field name\end_layout
\end_inset
</cell>
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\begin_inset Text
\begin_layout Plain Layout
......@@ -24599,27 +24635,27 @@ Reserved\end_layout
\end_inset
</cell>
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<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
TXTS\end_layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
TXT2E\end_layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
TXT1E\end_layout
Reserved\end_layout
\end_inset
</cell>
......@@ -24677,7 +24713,7 @@ Reset value\end_layout
\begin_inset Text
\begin_layout Plain Layout
X\end_layout
-\end_layout
\end_inset
</cell>
......@@ -24685,7 +24721,7 @@ X\end_layout
\begin_inset Text
\begin_layout Plain Layout
1\end_layout
-\end_layout
\end_inset
</cell>
......@@ -24693,7 +24729,7 @@ X\end_layout
\begin_inset Text
\begin_layout Plain Layout
1\end_layout
-\end_layout
\end_inset
</cell>
......@@ -24703,41 +24739,6 @@ X\end_layout
\end_inset
\end_layout
\begin_layout Description
TXT1E Active when Transmit buffer 1 is empty.
\end_layout
\begin_layout Description
TXT2E Active when Transmit buffer 2 is empty.
\end_layout
\begin_layout Description
TXTS Logic 1 if the core was synthesized wih "tx_time_support=true".Otherwise logic 0.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout Subsection
TX_SETTINGS
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
label{TX_SETTINGS
}\end_layout
\end_inset
\end_layout
\begin_layout Description
Type: read-write
\end_layout
\begin_layout Description
Address: 0x5C
\end_layout
\begin_layout Description
Size: 1 byte
\end_layout
\begin_layout Standard
This register controls the access into TX buffers. All bits are active in logic 1.
\end_layout
\begin_layout Standard
\noindent
......@@ -24767,7 +24768,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
7\end_layout
23\end_layout
\end_inset
</cell>
......@@ -24775,7 +24776,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
6\end_layout
22\end_layout
\end_inset
</cell>
......@@ -24783,7 +24784,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
5\end_layout
21\end_layout
\end_inset
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......@@ -24791,7 +24792,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
4\end_layout
20\end_layout
\end_inset
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......@@ -24799,7 +24800,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
3\end_layout
19\end_layout
\end_inset
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......@@ -24807,7 +24808,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
2\end_layout
18\end_layout
\end_inset
</cell>
......@@ -24815,7 +24816,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
1\end_layout
17\end_layout
\end_inset
</cell>
......@@ -24823,7 +24824,7 @@ Bit index\end_layout
\begin_inset Text
\begin_layout Plain Layout
0\end_layout
16\end_layout
\end_inset
</cell>
......@@ -24869,27 +24870,27 @@ Reserved\end_layout
\end_inset
</cell>
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<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
FRSW\end_layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
BDIR\end_layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
TXT2A\end_layout
Reserved\end_layout
\end_inset
</cell>
......@@ -24897,7 +24898,7 @@ TXT2A\end_layout
\begin_inset Text
\begin_layout Plain Layout
TXT1A\end_layout
TXTS\end_layout
\end_inset
</cell>
......@@ -24947,7 +24948,7 @@ Reset value\end_layout
\begin_inset Text
\begin_layout Plain Layout
0\end_layout
-\end_layout
\end_inset
</cell>
......@@ -24955,7 +24956,7 @@ Reset value\end_layout
\begin_inset Text
\begin_layout Plain Layout
0\end_layout
-\end_layout
\end_inset
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......@@ -24963,7 +24964,7 @@ Reset value\end_layout
\begin_inset Text
\begin_layout Plain Layout
0\end_layout
-\end_layout
\end_inset
</cell>
......@@ -24971,7 +24972,7 @@ Reset value\end_layout
\begin_inset Text
\begin_layout Plain Layout
0\end_layout
X\end_layout
\end_inset
</cell>
......@@ -24982,17 +24983,1522 @@ Reset value\end_layout
\end_layout
\begin_layout Description
TXT1A Allow transmitting frames from TXT buffer 1. Content of TX Buffer1 is validated by 0 to 1 transition on these bits.
\end_layout
\begin_layout Description
TXT2A Allow transmitting frames from TXT buffer 2. Content of TX Buffer2 is validated by 0 to 1 transition on these bits.
\end_layout
\begin_layout Description
BDIR Buffer to which the transmit data should be stored. To insert data for transmission first set TXT[n]A to 0, then set BDIR to select TXT buffer. As next write the data into buffer by executing accesses into TX_DATA_X registers. As last step, validate the content of the buffer by setting TXT[n] to 1. TXT[n]E bit of TX_STAT register is automatically cleared by this action.
\end_layout
\begin_layout Description
FRSW If frame is inserted into either TXT buffer and the other TXT buffer is empty, the frame in the first buffer is transmitted. However, if during the transmission of this frame another frame is inserted into the other TXT buffer and error occurs (or arbitration is lost) there are two frames which can be selected for transmission (assuming Timestamps of both frames are lower than external Timestamp) . If FRSW bit is set to 0 the frame which was transmitted last is rettransmitted. If FRSW is set to 1 the frame for transmission is selected as if both frames were inserted for its first transmission as explained in Section "Transmitt frame selection".
\begin_layout Standard
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="9" rows="3" version="3">
<features tabularvalignment="middle">
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Bit index\end_layout
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