Commit 44af491e authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added TXT Buffer priority and Status to the register map.

parent 06674422
This diff is collapsed.
......@@ -612,13 +612,19 @@ union tx_status {
#ifdef __BIG_ENDIAN_BITFIELD
/* TX_STATUS */
uint32_t txt1e : 1;
uint32_t txt1ts : 1;
uint32_t txt2e : 1;
uint32_t txt2ts : 1;
uint32_t reserved_15_4 : 12;
uint32_t txts : 1;
uint32_t reserved_31_3 : 29;
uint32_t reserved_31_17 : 15;
#else
uint32_t reserved_31_3 : 29;
uint32_t reserved_31_17 : 15;
uint32_t txts : 1;
uint32_t reserved_15_4 : 12;
uint32_t txt2ts : 1;
uint32_t txt2e : 1;
uint32_t txt1ts : 1;
uint32_t txt1e : 1;
#endif
} s;
......@@ -628,18 +634,26 @@ union tx_settings {
uint32_t u32;
struct tx_settings_s {
#ifdef __BIG_ENDIAN_BITFIELD
uint32_t reserved_1_0 : 2;
/* TX_SETTINGS */
uint32_t txt1a : 1;
uint32_t txt2a : 1;
uint32_t bdir : 1;
uint32_t frsw : 1;
uint32_t reserved_31_4 : 28;
uint32_t reserved_15_4 : 12;
uint32_t txt1a : 1;
uint32_t txt1p : 3;
uint32_t txt2a : 1;
uint32_t txt2p : 3;
uint32_t reserved_31_24 : 8;
#else
uint32_t reserved_31_4 : 28;
uint32_t frsw : 1;
uint32_t bdir : 1;
uint32_t reserved_31_24 : 8;
uint32_t txt2p : 3;
uint32_t txt2a : 1;
uint32_t txt1p : 3;
uint32_t txt1a : 1;
uint32_t reserved_15_4 : 12;
uint32_t frsw : 1;
uint32_t bdir : 1;
uint32_t reserved_1_0 : 2;
#endif
} s;
};
......
......@@ -1208,14 +1208,14 @@
<ipxact:description>This register controls the access into TX buffers. All bits are active in logic 1.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h5C</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-write</ipxact:access>
<ipxact:field>
<ipxact:name>TXT1A</ipxact:name>
<ipxact:displayName>TXT1A</ipxact:displayName>
<ipxact:description>Allow transmitting frames from TXT buffer 1. Content of TX Buffer1 is validated by 0 to 1 transition on these bits.</ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:description>Allow transmitting frames from TXT Buffer 1. Content of TX Buffer1 is validated by 0 to 1 transition on these bits.</ipxact:description>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
......@@ -1226,8 +1226,8 @@
<ipxact:field>
<ipxact:name>TXT2A</ipxact:name>
<ipxact:displayName>TXT2A</ipxact:displayName>
<ipxact:description>Allow transmitting frames from TXT buffer 2. Content of TX Buffer2 is validated by 0 to 1 transition on these bits.</ipxact:description>
<ipxact:bitOffset>1</ipxact:bitOffset>
<ipxact:description>Allow transmitting frames from TXT Buffer 2. Content of TX Buffer2 is validated by 0 to 1 transition on these bits.</ipxact:description>
<ipxact:bitOffset>20</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
......@@ -1259,6 +1259,30 @@
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>TXT1P</ipxact:name>
<ipxact:displayName>TXT1P</ipxact:displayName>
<ipxact:description>Priority of TXT Buffer 1.</ipxact:description>
<ipxact:bitOffset>17</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>1</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>3</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>TXT2P</ipxact:name>
<ipxact:displayName>TXT2P</ipxact:displayName>
<ipxact:description>Priority of TXT Buffer 2.</ipxact:description>
<ipxact:bitOffset>21</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>3</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>LOG_TRIG_CONFIG</ipxact:name>
......@@ -2353,17 +2377,17 @@
<ipxact:register>
<ipxact:name>TX_STATUS</ipxact:name>
<ipxact:displayName>TX_STATUS</ipxact:displayName>
<ipxact:description>Status of the TXT Buffers. </ipxact:description>
<ipxact:description>Status of TXT Buffers. </ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h58</ipxact:addressOffset>
<ipxact:size>8</ipxact:size>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-only</ipxact:access>
<ipxact:field>
<ipxact:name>TXT2E</ipxact:name>
<ipxact:displayName>TXT2E</ipxact:displayName>
<ipxact:description>Active when Transmit buffer 2 is empty.</ipxact:description>
<ipxact:bitOffset>1</ipxact:bitOffset>
<ipxact:bitOffset>2</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>1</ipxact:value>
......@@ -2387,7 +2411,31 @@
<ipxact:name>TXTS</ipxact:name>
<ipxact:displayName>TXTS</ipxact:displayName>
<ipxact:description>Logic 1 if the core was synthesized wih &quot;tx_time_support=true&quot;.Otherwise logic 0.</ipxact:description>
<ipxact:bitOffset>2</ipxact:bitOffset>
<ipxact:bitOffset>16</ipxact:bitOffset>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>TXT1TS</ipxact:name>
<ipxact:displayName>TXT1TS</ipxact:displayName>
<ipxact:description>Transmission from TXT Buffer 1 was succesfull. This bit is set together with TXT1E.</ipxact:description>
<ipxact:bitOffset>1</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>TXT2TS</ipxact:name>
<ipxact:displayName>TXT2TS</ipxact:displayName>
<ipxact:description>Transmission from TXT Buffer 2 was succesfull. This bit is set together with TXT2E.</ipxact:description>
<ipxact:bitOffset>3</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
......
......@@ -785,15 +785,19 @@ package CAN_FD_register_map is
------------------------------------------------------------------------------
-- TX_STATUS register
--
-- Status of the TXT Buffers.
-- Status of TXT Buffers.
------------------------------------------------------------------------------
constant TXT1E_IND : natural := 0;
constant TXT2E_IND : natural := 1;
constant TXTS_IND : natural := 2;
constant TXT1TS_IND : natural := 1;
constant TXT2E_IND : natural := 2;
constant TXT2TS_IND : natural := 3;
constant TXTS_IND : natural := 16;
-- TX_STATUS register reset values
constant TXT2E_RSTVAL : std_logic := '1';
constant TXT1E_RSTVAL : std_logic := '1';
constant TXT1TS_RSTVAL : std_logic := '0';
constant TXT2TS_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
-- TX_SETTINGS register
......@@ -801,16 +805,22 @@ package CAN_FD_register_map is
-- This register controls the access into TX buffers. All bits are active in l
-- ogic 1.
------------------------------------------------------------------------------
constant TXT1A_IND : natural := 0;
constant TXT2A_IND : natural := 1;
constant BDIR_IND : natural := 2;
constant FRSW_IND : natural := 3;
constant TXT1A_IND : natural := 16;
constant TXT1P_L : natural := 17;
constant TXT1P_H : natural := 19;
constant TXT2A_IND : natural := 20;
constant TXT2P_L : natural := 21;
constant TXT2P_H : natural := 23;
-- TX_SETTINGS register reset values
constant TXT1A_RSTVAL : std_logic := '0';
constant TXT2A_RSTVAL : std_logic := '0';
constant BDIR_RSTVAL : std_logic := '0';
constant FRSW_RSTVAL : std_logic := '0';
constant TXT1P_RSTVAL : std_logic_vector(2 downto 0) := "001";
constant TXT2P_RSTVAL : std_logic_vector(2 downto 0) := "000";
------------------------------------------------------------------------------
-- ERR_CAPT register
......
......@@ -105,6 +105,15 @@ package CANconstants is
constant INC_EIGHT_CON : std_logic_vector(2 downto 0) := "010";
constant DEC_ONE_CON : std_logic_vector(2 downto 0) := "001";
constant TXT_BUFFER_COUNT : natural := 2;
-- TXT Buffer settings indices
type txt_buf_settings_type is array (1 to TXT_BUFFER_COUNT) of
std_logic_vector(3 downto 0);
constant TXTB_ALLOW_I : natural := 0;
constant TXTB_PRIORITY_H : natural := 3;
constant TXTB_PRIORITY_L : natural := 1;
--Values for enabling of whole controller
--and interrupts
--constant ENABLED : std_logic := '1';
......
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