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CTU CAN FD IP Core
Commit 444bc2a9 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Merge branch '170-unify-others-clause' into 'master' 

Resolve "Unify "others" clause!"

Closes #170

See merge request illeondr/CAN_FD_IP_Core!129
parents e19075e3 73a51f21
Pipeline #1561 passed with stages
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        src/CAN_Core/core_top.vhd
        View file @ 444bc2a9
        ......@@ -391,6 +391,8 @@ entity core_top is
        signal is_idle : std_logic;
        signal alc : std_logic_vector(7 downto 0);
        signal unknown_OP_state : std_logic;
        -- Transcieve buffer output
        signal tran_dlc : std_logic_vector(3 downto 0);
        signal tran_is_rtr : std_logic;
        ......@@ -590,6 +592,7 @@ begin
        tran_data_valid_in => tran_frame_valid_in,
        set_transciever => set_transciever,
        set_reciever => set_reciever,
        unknown_OP_state => unknown_OP_state,
        is_idle => is_idle,
        tran_trig => tran_trig,
        rec_trig => rec_trig,
        ......@@ -651,7 +654,6 @@ begin
        form_Error => form_Error,
        CRC_Error => CRC_Error,
        ack_Error => ack_Error,
        unknown_state_Error => unknown_state_Error,
        bit_Error_valid => bit_Error_valid,
        stuff_Error_valid => stuff_Error_valid,
        ......@@ -678,6 +680,8 @@ begin
        destuff_length => bds_length,
        dst_ctr => st_ctr_resolved,
        unknown_OP_state => unknown_OP_state,
        crc_enable => crc_enable,
        crc15 => crc15,
        crc17 => crc17,
        ......@@ -728,7 +732,6 @@ begin
        form_Error => form_Error,
        CRC_Error => CRC_Error,
        ack_Error => ack_Error,
        unknown_state_Error => unknown_state_Error,
        bit_Error_valid => bit_Error_valid,
        stuff_Error_valid => stuff_Error_valid,
        ......@@ -957,9 +960,9 @@ begin
        ----------------------------------------------------------------------------
        -- Multiplexing of stuff counter and destuff counter
        ----------------------------------------------------------------------------
        st_ctr_resolved <= dst_ctr when OP_State = reciever else
        bst_ctr when OP_State = transciever else
        0;
        st_ctr_resolved <= dst_ctr when (OP_State = reciever) else
        bst_ctr when (OP_State = transciever) else
        0;
        ----------------------------------------------------------------------------
        ......@@ -1010,14 +1013,14 @@ begin
        -- detection during Data Phase!!!
        ----------------------------------------------------------------------------
        bs_trig <= sync_nbt_del_1 when sp_control_int = NOMINAL_SAMPLE else
        sync_dbt_del_1 when sp_control_int = DATA_SAMPLE else
        sync_dbt_del_1 when sp_control_int = SECONDARY_SAMPLE else
        bs_trig <= sync_nbt_del_1 when (sp_control_int = NOMINAL_SAMPLE) else
        sync_dbt_del_1 when (sp_control_int = DATA_SAMPLE) else
        sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
        '0';
        bds_trig <= sample_nbt_del_1 when sp_control_int = NOMINAL_SAMPLE else
        sample_dbt_del_1 when sp_control_int = DATA_SAMPLE else
        sync_dbt_del_1 when sp_control_int = SECONDARY_SAMPLE else
        bds_trig <= sample_nbt_del_1 when (sp_control_int = NOMINAL_SAMPLE) else
        sample_dbt_del_1 when (sp_control_int = DATA_SAMPLE) else
        sync_dbt_del_1 when (sp_control_int = SECONDARY_SAMPLE) else
        '0';
        ----------------------------------------------------------------------------
        ......@@ -1055,9 +1058,9 @@ begin
        else rec_trig;
        crc_tx_wbs_trig <= '0' when (fixed_stuff = '1' and data_halt = '1') else
        sync_nbt_del_2 when sp_control_int = NOMINAL_SAMPLE else
        sync_dbt_del_2 when sp_control_int = DATA_SAMPLE else
        sync_dbt_del_2 when sp_control_int = SECONDARY_SAMPLE else
        sync_nbt_del_2 when (sp_control_int = NOMINAL_SAMPLE) else
        sync_dbt_del_2 when (sp_control_int = DATA_SAMPLE) else
        sync_dbt_del_2 when (sp_control_int = SECONDARY_SAMPLE) else
        '0';
        error_valid <= error_valid_int;
        ......@@ -1203,7 +1206,7 @@ begin
        stat_bus(STAT_FORM_ERROR_INDEX) <= form_Error;
        stat_bus(STAT_CRC_ERROR_INDEX) <= CRC_Error;
        stat_bus(STAT_ACK_ERROR_INDEX) <= ack_Error;
        stat_bus(STAT_UNKNOWN_STATE_ERROR_INDEX) <= unknown_state_Error;
        stat_bus(STAT_UNKNOWN_STATE_ERROR_INDEX) <= '0';
        stat_bus(STAT_BIT_STUFF_ERROR_INDEX)
        <= bit_Error_valid or stuff_Error_valid;
        ......
        src/CAN_Core/faultConf.vhd
        View file @ 444bc2a9
        ......@@ -127,10 +127,6 @@ entity faultConf is
        signal CRC_Error :in std_logic; --CRC Error from PC State
        signal ack_Error :in std_logic; --Acknowledge Error from PC
        -- Some of the state machines, or signals
        -- reached unknown state!! Shouldnt happend!!
        signal unknown_state_Error :in std_logic;
        -- Error signal for PC control FSM from fault
        -- confinement unit (Bit error or Stuff Error appeared)
        signal bit_Error_valid :out std_logic;
        ......
        src/CAN_Core/operationControl.vhd
        View file @ 444bc2a9
        ......@@ -77,6 +77,8 @@ entity operationControl is
        signal is_idle :in std_logic; --Unit is idle
        signal unknown_OP_state :out std_logic;
        -- Bit time triggering signals
        signal tran_trig :in std_logic;
        signal rec_trig :in std_logic;
        ......@@ -111,10 +113,13 @@ begin
        if (res_n = ACT_RESET) then
        OP_State_r <= integrating;
        integ_counter <= 1;
        unknown_OP_state <= '0';
        elsif rising_edge(clk_sys) then
        -- Presetting the registers to avoid latches
        OP_State_r <= OP_State_r;
        integ_counter <= integ_counter;
        unknown_OP_state <= '0';
        if (set_transciever = '1') then
        OP_State_r <= transciever;
        ......@@ -180,7 +185,7 @@ begin
        OP_State_r <= idle;
        end if;
        when others =>
        report "Unknown operational state" severity failure;
        unknown_OP_state <= '1';
        end case;
        end if;
        end if;
        ......
        src/CAN_Core/protocolControl.vhd
        View file @ 444bc2a9
        ......@@ -216,6 +216,18 @@
        -- 10.7.2018 Changed length of data length field for DLC > 8 in case of
        -- CAN 2.0 frame! For CAN 2.0 frame DLC higher than 8 should be
        -- interpreted as 8!
        -- 13.7.2018 Removed "unknown_state_Error_r" since it was unused. Unified
        -- all "when others" statements to go to "error" state an cause
        -- error frame transmission! This is however synthesis tool
        -- dependent! If FSM synthesis on invalid state (e.g. glitch)
        -- would jump to reset state, then node would become off, and
        -- communication would not continue! If synthesis tool would
        -- use "others" to detect invalid FSM state, and go to "error"
        -- state, then this would be "safety" feature for possible
        -- glitches. From CAN Node perspective, this would be another
        -- "internal" error, which would cause transmission of error
        -- frame! Such a behaviour is not defined by standard, but it
        -- is logical to do it like so!
        --------------------------------------------------------------------------------
        Library ieee;
        ......@@ -303,6 +315,9 @@ entity protocolControl is
        --Arbitration lost capture
        signal alc :out std_logic_vector(7 downto 0);
        --Unknown Operational state -> Error frame!
        signal unknown_OP_state :in std_logic;
        -------------------------------
        --Fault confinement Interface--
        ......@@ -313,11 +328,7 @@ entity protocolControl is
        --Error signals for fault confinement
        signal form_Error :out std_logic; --Form Error
        signal CRC_Error :out std_logic; --CRC Error
        signal ack_Error :out std_logic; --Acknowledge error
        --Some of the state machines,
        --or signals reached unknown state!!
        signal unknown_state_Error :out std_logic;
        signal ack_Error :out std_logic; --Acknowledge error
        --Error signal for PC control FSM from fault confinement
        --unit (Bit error or Stuff Error appeared)
        ......@@ -510,7 +521,6 @@ entity protocolControl is
        signal form_Error_r : std_logic; --Form Error
        signal CRC_Error_r : std_logic; --CRC Error
        signal ack_Error_r : std_logic; --Acknowledge error
        signal unknown_state_Error_r : std_logic; --Unknown state Error
        signal inc_one_r : std_logic;
        signal inc_eight_r : std_logic;
        ......@@ -758,7 +768,6 @@ begin
        form_Error <= form_Error_r;
        CRC_Error <= CRC_Error_r;
        ack_Error <= ack_Error_r;
        unknown_state_Error <= unknown_state_Error_r;
        int_loop_back_ena <= int_loop_back_ena_r;
        inc_one <= inc_one_r;
        ......@@ -941,14 +950,14 @@ begin
        --Prestting internal registers--
        --------------------------------
        rec_brs_r <= '0';
        rec_crc_r <= (OTHERS=>'0');
        rec_crc_r <= (OTHERS => '0');
        rec_esi_r <= '0';
        arb_two_bits <= (OTHERS=>'0');
        arb_two_bits <= (OTHERS => '0');
        arb_one_bit <= '0';
        ctrl_tran_reg <= (OTHERS =>'0');
        dlc_int <= (OTHERS=>'0');
        ctrl_tran_reg <= (OTHERS => '0');
        dlc_int <= (OTHERS => '0');
        crc_src <= "11";
        crc_check <= '0';
        ......@@ -957,7 +966,7 @@ begin
        sec_ack <= '0';
        tran_pointer <= 0;
        alc_r <= (OTHERS=>'0');
        alc_r <= (OTHERS => '0');
        data_pointer <= 0;
        data_tx_index <= 0;
        ......@@ -966,9 +975,9 @@ begin
        tran_ident_ext_sr <= (OTHERS => '0');
        -- Nulling recieve registers
        rec_ident_base_sr <= (OTHERS=>'0');
        rec_ident_ext_sr <= (OTHERS=>'0');
        rec_dlc_r <= (OTHERS=>'0');
        rec_ident_base_sr <= (OTHERS => '0');
        rec_ident_ext_sr <= (OTHERS => '0');
        rec_dlc_r <= (OTHERS => '0');
        rec_is_rtr_r <= '0';
        rec_ident_type_r <= '0';
        rec_frame_type_r <= '0';
        ......@@ -977,7 +986,7 @@ begin
        store_metadata_r <= '0';
        rec_abort_r <= '0';
        store_data_r <= '0';
        store_data_word_r <= (OTHERS=>'0');
        store_data_word_r <= (OTHERS => '0');
        -- Receive data RAM
        rec_word_ptr <= 0;
        ......@@ -1001,14 +1010,13 @@ begin
        form_Error_r <= '0';
        CRC_Error_r <= '0';
        ack_Error_r <= '0';
        unknown_state_Error_r <= '0';
        set_transciever_r <= '0';
        set_reciever_r <= '0';
        delay_control_trans <= '0';
        rx_parity <= '0';
        rx_count_grey <= (OTHERS =>'0');
        rx_count_grey <= (OTHERS => '0');
        sof_pulse_r <= '0';
        ......@@ -1117,7 +1125,6 @@ begin
        form_Error_r <= '0';
        CRC_Error_r <= '0';
        ack_Error_r <= '0';
        unknown_state_Error_r <= '0';
        int_loop_back_ena_r <= int_loop_back_ena_r;
        crc_state <= crc_state;
        ......@@ -1156,7 +1163,9 @@ begin
        if (drv_ena = '0') then
        PC_State <= off;
        elsif (bit_Error_valid = '1' or stuff_Error_valid = '1') then
        elsif (bit_Error_valid = '1' or stuff_Error_valid = '1' or
        unknown_OP_state = '1')
        then
        PC_State <= error;
        FSM_preset <= '1';
        ......@@ -1218,17 +1227,17 @@ begin
        control_pointer <= 0;
        -- Erasing the recieved for ID and metadata
        rec_ident_base_sr <= (OTHERS =>'0');
        rec_ident_ext_sr <= (OTHERS =>'0');
        rec_dlc_r <= (OTHERS =>'0');
        rec_ident_base_sr <= (OTHERS => '0');
        rec_ident_ext_sr <= (OTHERS => '0');
        rec_dlc_r <= (OTHERS => '0');
        rec_is_rtr_r <= '0';
        rec_ident_type_r <= '0';
        rec_frame_type_r <= '0';
        rec_brs_r <= '0';
        rec_crc_r <= (OTHERS =>'0');
        rec_crc_r <= (OTHERS => '0');
        rec_esi_r <= '0';
        rx_parity <= '0';
        rx_count_grey <= (OTHERS =>'0');
        rx_count_grey <= (OTHERS => '0');
        -- Erasing internal DLC
        dlc_int <= (OTHERS => '0');
        ......@@ -1401,8 +1410,7 @@ begin
        when RECESSIVE_RECESSIVE =>
        when DOMINANT_DOMINANT =>
        when others =>
        unknown_state_Error_r <= '1';
        when others =>
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -1487,7 +1495,6 @@ begin
        -- Error if undefined
        when others =>
        data_tx_r <= RECESSIVE;
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -1626,7 +1633,6 @@ begin
        end if;
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -1740,7 +1746,6 @@ begin
        control_pointer <= 7;
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -2023,8 +2028,7 @@ begin
        --------------------------------------------------------
        store_metadata_r <= '1';
        when others =>
        unknown_state_Error_r <= '1';
        when others =>
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -2064,7 +2068,6 @@ begin
        when "1111" => data_pointer <= 511; -- 64 bytes
        when others =>
        data_pointer <= 0;
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -2148,7 +2151,6 @@ begin
        rec_data_sr(6 downto 0) &
        data_rx;
        when others =>
        report "Unknown state" severity error;
        PC_State <= error;
        FSM_Preset <= '1';
        end case;
        ......@@ -2256,7 +2258,6 @@ begin
        rec_crc_r <= (OTHERS => '0');
        FSM_Preset <= '0';
        else
        case crc_state is
        ......@@ -2308,9 +2309,8 @@ begin
        when CRC_21_SRC =>
        data_tx_r <= crc21(data_pointer);
        when others=>
        data_tx_r <= data_tx_r;
        unknown_state_Error_r <= '1';
        when others =>
        data_tx_r <= RECESSIVE;
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -2330,6 +2330,8 @@ begin
        end if;
        when others =>
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        end if;
        ......@@ -2443,7 +2445,6 @@ begin
        FSM_Preset <= '1';
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -2494,7 +2495,6 @@ begin
        int_loop_back_ena_r <= '0';
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -2553,6 +2553,8 @@ begin
        FSM_preset <= '1';
        when others =>
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        if (control_pointer_non_zero) then
        ......@@ -2799,7 +2801,6 @@ begin
        end if;
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......@@ -3064,7 +3065,6 @@ begin
        -- Other, invalid states!
        ----------------------------------------------------------------
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        int_loop_back_ena_r <= '0';
        ......@@ -3195,7 +3195,6 @@ begin
        end if;
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        int_loop_back_ena_r <= '0';
        ......@@ -3223,7 +3222,6 @@ begin
        ----------------------------------------------------------------------------
        ----------------------------------------------------------------------------
        when others =>
        unknown_state_Error_r <= '1';
        PC_State <= error;
        FSM_preset <= '1';
        end case;
        ......
        src/Libraries/CANcomponents.vhd
        View file @ 444bc2a9
        ......@@ -590,9 +590,10 @@ package CANcomponents is
        signal set_transciever : in std_logic;
        signal set_reciever : in std_logic;
        signal is_idle : in std_logic;
        signal unknown_OP_state : out std_logic;
        signal tran_trig : in std_logic;
        signal rec_trig : in std_logic;
        signal data_rx : std_logic;
        signal data_rx : in std_logic;
        signal OP_State : out oper_mode_type
        );
        end component;
        ......@@ -642,7 +643,6 @@ package CANcomponents is
        signal form_Error : out std_logic;
        signal CRC_Error : out std_logic;
        signal ack_Error : out std_logic;
        signal unknown_state_Error : out std_logic;
        signal bit_Error_valid : in std_logic;
        signal stuff_Error_valid : in std_logic;
        signal inc_one : out std_logic;
        ......@@ -663,6 +663,7 @@ package CANcomponents is
        signal destuff_length : out std_logic_vector(2 downto 0);
        signal dst_ctr : in natural range 0 to 7;
        signal crc_enable : out std_logic;
        signal unknown_OP_state : in std_logic;
        signal crc15 : in std_logic_vector(14 downto 0);
        signal crc17 : in std_logic_vector(16 downto 0);
        signal crc21 : in std_logic_vector(20 downto 0);
        ......@@ -699,7 +700,6 @@ package CANcomponents is
        signal form_Error : in std_logic;
        signal CRC_Error : in std_logic;
        signal ack_Error : in std_logic;
        signal unknown_state_Error : in std_logic;
        signal bit_Error_valid : out std_logic;
        signal stuff_Error_valid : out std_logic;
        signal inc_one : in std_logic;
        ......
        test/unit/Fault_confinement/Fault_confinement_tb.vhd
        View file @ 444bc2a9
        ......@@ -107,10 +107,6 @@ architecture Fault_Confinement_unit_test of CAN_test is
        -- Acknowledge Error from PC
        signal ack_Error : std_logic := '0';
        -- Some of the state machines, or signals
        -- reached unknown state!! Shouldnt happend!!
        signal unknown_state_Error : std_logic := '0';
        -- Error signal for PC control FSM from fault
        -- confinement unit (Bit error or Stuff Error appeared)
        signal bit_Error_valid : std_logic;
        ......@@ -197,7 +193,6 @@ begin
        form_Error => form_Error,
        CRC_Error => CRC_Error,
        ack_Error => ack_Error,
        unknown_state_Error => unknown_state_Error,
        bit_Error_valid => bit_Error_valid,
        stuff_Error_valid => stuff_Error_valid,
        bit_Error_out => bit_Error_out,
        ......
        test/unit/Protocol_Control/Protocol_Control_tb.vhd
        View file @ 444bc2a9
        ......@@ -113,7 +113,7 @@
        -- RX Storing protocol.
        -- 2. Added dynamically generated stuff lenght and SW model
        -- for grey coding of sutff length.
        --
        -- 13.7.2018 Added Unknown operational state signals!
        --------------------------------------------------------------------------------
        Library ieee;
        ......@@ -227,9 +227,6 @@ architecture Protocol_Control_unit_test of CAN_test is
        -- Acknowledge error
        signal ack_Error_1 : std_logic;
        -- Protocol control in unknown state
        signal unknown_state_Error_1 : std_logic;
        -- Bit error is valid
        signal bit_Error_valid_1 : std_logic;
        ......@@ -310,6 +307,9 @@ architecture Protocol_Control_unit_test of CAN_test is
        -- Internal loopBack enabled (for Bus monitoring mode)
        signal int_loop_back_ena_1 : std_logic;
        -- Unknown operational state
        signal unknown_OP_state_1 : std_logic;
        -- Protocol state output.
        signal PC_State_out_1 : protocol_type;
        ......@@ -393,9 +393,6 @@ architecture Protocol_Control_unit_test of CAN_test is
        -- Acknowledge error
        signal ack_Error_2 : std_logic;
        -- Protocol control in unknown state
        signal unknown_state_Error_2 : std_logic;
        -- Bit error is valid
        signal bit_Error_valid_2 : std_logic;
        ......@@ -477,6 +474,9 @@ architecture Protocol_Control_unit_test of CAN_test is
        -- Internal loopBack enabled (for Bus monitoring mode)
        signal int_loop_back_ena_2 : std_logic;
        -- Unknown operational state
        signal unknown_OP_state_2 : std_logic;
        -- Protocol state output.
        signal PC_State_out_2 : protocol_type;
        ......@@ -845,9 +845,9 @@ begin
        form_Error => form_Error_1,
        CRC_Error => CRC_Error_1,
        ack_Error => ack_Error_1,
        unknown_state_Error => unknown_state_Error_1,
        bit_Error_valid => bit_Error_valid_1,
        stuff_Error_valid => stuff_Error_valid_1,
        unknown_OP_state => unknown_OP_state_1,
        inc_one => inc_one_1,
        inc_eight => inc_eight_1,
        dec_one => dec_one_1,
        ......@@ -920,9 +920,9 @@ begin
        form_Error => form_Error_2,
        CRC_Error => CRC_Error_2,
        ack_Error => ack_Error_2,
        unknown_state_Error => unknown_state_Error_2,
        bit_Error_valid => bit_Error_valid_2,
        stuff_Error_valid => stuff_Error_valid_2,
        unknown_OP_state => unknown_OP_state_2,
        inc_one => inc_one_2,
        inc_eight => inc_eight_2,
        dec_one => dec_one_2,
        ......
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