Commit 42d6e899 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Fix mismatching port direction.

parent 398dc192
Pipeline #13762 passed with stages
in 19 minutes and 2 seconds
......@@ -243,7 +243,7 @@ package can_components is
sync_edge :out std_logic;
-- Time quanta edge
tq_edge :out std_logic;
tq_edge :in std_logic;
-- CAN Core Interface
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