Added byte enable support on on writes to the registers.

Read support remaining.

src/CAN_top_level.vhd

@@ -116,6 +116,7 @@ entity CAN_top_level is
     signal scs      : in  std_logic;    --Chip select
     signal srd      : in  std_logic;    --Serial read
     signal swr      : in  std_logic;    --Serial write
+    signal sbe      : in  std_logic_vector(3 downto 0);
     --Note: This bus is Avalon compatible!
 
     --------------------
@@ -489,6 +490,7 @@ begin
       scs                  => scs,
       srd                  => srd,
       swr                  => swr,
+      sbe                  => sbe,
       drv_bus              => drv_bus,
       stat_bus             => stat_bus,
       rx_read_buff         => rx_read_buff,

src/CANcomponents.vhd

@@ -85,6 +85,7 @@ package CANcomponents is
       signal scs             : in  std_logic;
       signal srd             : in  std_logic;
       signal swr             : in  std_logic;
+      signal sbe             : in  std_logic_vector(3 downto 0);
       signal int             : out std_logic;
       signal CAN_tx          : out std_logic;
       signal CAN_rx          : in  std_logic;
@@ -123,6 +124,7 @@ package CANcomponents is
       signal scs                  : in  std_logic;
       signal srd                  : in  std_logic;
       signal swr                  : in  std_logic;
+      signal sbe                  : in  std_logic_vector(3 downto 0);
       signal drv_bus              : out std_logic_vector(1023 downto 0);
       signal stat_bus             : in  std_logic_vector(511 downto 0);
       signal rx_read_buff         : in  std_logic_vector(31 downto 0);

synthesis/Quartus/CAN_Wrapper.vhd

@@ -73,6 +73,7 @@ entity CAN_Wrapper is
      signal scs      : in  std_logic;    --Chip select
      signal srd      : in  std_logic;    --Serial read
      signal swr      : in  std_logic;    --Serial write
+	  signal sbe      : in  std_logic_vector(3 downto 0); --BE
      
 	  signal int : out std_logic;
 
@@ -222,6 +223,7 @@ begin
      scs            => scs,
      srd            => srd,
      swr            => swr,
+	  sbe			     => sbe,
      int            => int,
      CAN_tx         => CAN_tx,
      CAN_rx         => CAN_rx,

test/feature/feature_env.vhd

@@ -76,7 +76,7 @@ architecture feature_env_test of CAN_feature_test is
   	 signal scs_1: std_logic:= '0'; --Chip select
     signal srd_1: std_logic:= '0'; --Serial read
     signal swr_1: std_logic:= '0'; --Serial write
-      
+    signal sbe_1: std_logic_vector(3 downto 0) := (OTHERS => '1'); --Byte enable
   
     --Controller 2 signals
     signal clk_sys_2          : std_logic:= '0';
@@ -93,7 +93,7 @@ architecture feature_env_test of CAN_feature_test is
   	 signal scs_2: std_logic:= '0'; --Chip select
     signal srd_2: std_logic:= '0'; --Serial read
     signal swr_2: std_logic:= '0'; --Serial write
-    
+    signal sbe_2: std_logic_vector(3 downto 0) := (OTHERS => '1'); --Byte enable
     
     --------------------------------------------------
     --------------------------------------------------
@@ -134,6 +134,7 @@ begin
     	  scs                =>  scs_1,
        srd                =>  srd_1,
        swr                =>  swr_1,
+       sbe                =>  sbe_1,
        int                =>  int_1,
        CAN_tx             =>  CAN_tx_1,
        CAN_rx             =>  CAN_rx_1,
@@ -159,6 +160,7 @@ begin
     	  scs                =>  scs_2,
        srd                =>  srd_2,
        swr                =>  swr_2,
+       sbe                =>  sbe_2,
        int                =>  int_2,
        CAN_tx             =>  CAN_tx_2,
        CAN_rx             =>  CAN_rx_2,

test/sanity/sanity_test.vhd

@@ -113,6 +113,7 @@ architecture sanity_test of CAN_test is
   -- record types to components!
   type mem_vect_arr_type is array (1 to NODE_COUNT) of std_logic_vector(31 downto 0);
   type mem_contr_arr_type is array (1 to NODE_COUNT) of std_logic;
+  type mem_be_arr_type is array (1 to NODE_COUNT) of std_logic_vector(3 downto 0);
   type mem_addr_arr_type is array (1 to NODE_COUNT) of std_logic_vector(23 downto 0); 
   signal mem_aux_data_in      : mem_vect_arr_type := (OTHERS => (OTHERS => '0'));
   signal mem_aux_data_out     : mem_vect_arr_type := (OTHERS => (OTHERS => '0'));
@@ -120,6 +121,7 @@ architecture sanity_test of CAN_test is
   signal mem_aux_scs          : mem_contr_arr_type := (OTHERS => '0');
   signal mem_aux_swr          : mem_contr_arr_type := (OTHERS => '0');
   signal mem_aux_srd          : mem_contr_arr_type := (OTHERS => '0');
+  signal mem_aux_sbe          : mem_be_arr_type := (OTHERS => (OTHERS => '1')); -- By default all accesses as 32 bit
   signal mem_aux_clk          : mem_contr_arr_type := (OTHERS => '0');
   
   signal res_n_v              : std_logic_vector(1 to NODE_COUNT) := (OTHERS => '0');
@@ -424,6 +426,7 @@ begin
       	  scs              => mem_aux_scs(i),
          srd              => mem_aux_srd(i),
          swr              => mem_aux_swr(i),
+         sbe              => mem_aux_sbe(i),
          int              => int_v(i),
          CAN_tx           => CAN_tx_v(i),
          CAN_rx           => CAN_rx_v(i),