Commit 405113fb authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Prescaler clean-up. Move no_pos_resync to CAN Core directly.

parent 812c01b7
......@@ -255,7 +255,10 @@ entity can_core is
-- trigger signal therefore logically belongs here
-- Synchronisation control signal (Hard sync, Re Sync)
signal sync_control :out std_logic_vector(1 downto 0);
signal sync_control :out std_logic_vector(1 downto 0);
-- No positive resynchronisation
signal no_pos_resync :out std_logic;
------------------------------------------------------------------------
-- Recieve and transcieved data interface
......@@ -1003,6 +1006,15 @@ begin
drv_int_loopback_ena = '1')
else
data_tx_from_PC;
----------------------------------------------------------------------------
-- No positive resynchronisation for transceiver due to RECESSIVE to
-- DOMINANT transition.
----------------------------------------------------------------------------
no_pos_resync <= '1' when (OP_State = transciever and data_tx = DOMINANT)
else
'0';
----------------------------------------------------------------------------
......
......@@ -411,13 +411,7 @@ architecture rtl of CAN_top_level is
--Protocol control state
signal OP_State : oper_mode_type;
--Time quantum clock - Nominal bit time
signal clk_tq_nbt : std_logic;
--Bit time - Nominal bit time
signal clk_tq_dbt : std_logic;
--Sample signal for nominal bit time
signal sample_nbt : std_logic;
......@@ -447,12 +441,10 @@ architecture rtl of CAN_top_level is
signal bt_FSM_out : bit_time_type;
--Validated hard synchronisation edge to start Protocol control FSM
-- Validated hard synchronisation edge to start Protocol control FSM
signal hard_sync_edge_valid : std_logic;
--Note: Sync edge from busSync.vhd cant be used! If it comes during sample
-- nbt, sequence it causes errors! It needs to be strictly before or
-- strictly after this sequence!!!
signal no_pos_resync : std_logic;
----------------------------------------------------------------------------
-- Bus Synchroniser Interface
......@@ -770,6 +762,7 @@ begin
sample_sec_del_1 => sample_sec_del_1,
sample_sec_del_2 => sample_sec_del_2,
sync_control => sync_control,
no_pos_resync => no_pos_resync,
data_rx => data_rx,
data_tx => data_tx,
timestamp => timestamp,
......@@ -808,20 +801,18 @@ begin
port map(
clk_sys => clk_sys,
res_n => res_n_int,
OP_State => OP_State,
sync_edge => sync_edge,
drv_bus => drv_bus,
clk_tq_nbt => clk_tq_nbt,
clk_tq_dbt => clk_tq_dbt,
sample_nbt => sample_nbt_i,
sample_dbt => sample_dbt_i,
bt_FSM_out => bt_FSM_out,
sync_nbt => sync_nbt_i,
sync_dbt => sync_dbt_i,
data_tx => data_tx,
time_quanta_clk => time_quanta_clk,
hard_sync_edge_valid => hard_sync_edge_valid,
sp_control => sp_control,
sync_control => sync_control
sync_control => sync_control,
no_pos_resync => no_pos_resync
);
-- Temporary internal connections. Will be replaced during protocol
......@@ -904,10 +895,6 @@ begin
log_state_out <= config;
end generate event_logger_gen_false;
--Bit time clock output propagation
time_quanta_clk <= clk_tq_nbt when sp_control = NOMINAL_SAMPLE else
clk_tq_dbt;
OP_State <= oper_mode_type'val(to_integer(unsigned(
stat_bus(STAT_OP_STATE_HIGH downto STAT_OP_STATE_LOW))));
......
......@@ -663,6 +663,7 @@ package can_components is
signal sample_sec_del_1 : in std_logic;
signal sample_sec_del_2 : in std_logic;
signal sync_control : out std_logic_vector(1 downto 0);
signal no_pos_resync : out std_logic;
signal data_rx : in std_logic;
signal data_tx : out std_logic;
signal timestamp : in std_logic_vector(63 downto 0);
......@@ -719,19 +720,17 @@ package can_components is
signal clk_sys : in std_logic;
signal res_n : in std_logic;
signal sync_edge : in std_logic;
signal OP_State : in oper_mode_type;
signal drv_bus : in std_logic_vector(1023 downto 0);
signal clk_tq_nbt : out std_logic;
signal clk_tq_dbt : out std_logic;
signal sample_nbt : out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sample_dbt : out std_logic_vector(sample_trigger_count - 1 downto 0);
signal sync_nbt : out std_logic_vector(sync_trigger_count - 1 downto 0);
signal sync_dbt : out std_logic_vector(sync_trigger_count - 1 downto 0);
signal time_quanta_clk : out std_logic;
signal bt_FSM_out : out bit_time_type;
signal data_tx : in std_logic;
signal hard_sync_edge_valid : out std_logic;
signal sp_control : in std_logic_vector(1 downto 0);
signal sync_control : in std_logic_vector(1 downto 0)
signal sync_control : in std_logic_vector(1 downto 0);
signal no_pos_resync : in std_logic
);
end component;
......
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