Commit 3f9b25ee authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '342-debug-nightly-run' into 'master'

Resolve "Debug nightly run"

Closes #342

See merge request !302
parents 681723e5 085599b4
......@@ -240,10 +240,21 @@ package body alc_srr_rtr_feature is
check(iout(2).can_tx = RECESSIVE, "Recessive RTR transmitted!");
wait for 20 ns; -- To account for trigger processing
get_controller_status(stat_2, ID_2, mem_bus(2));
check(stat_2.receiver, "Node 2 lost arbitration!");
get_controller_status(stat_1, ID_1, mem_bus(1));
check(stat_1.transmitter, "Node 1 transmitter!");
-- This wait is needed since we waited for RX Trigger of Node 1.
-- Node 2 could have not reached RX Trigger yet! To be sure, we
-- wait one more RX Trigger of Node 2! If Node 2 RX Trigger was earlier,
-- we wait till next bit (which does not mind since we lost arbitration
-- already and we need it for check of operational state only). If
-- Node 2 RX Trigger was later, we get right behind the sample point
-- where we should have lost arbitration!
CAN_wait_sample_point(iout(2).stat_bus);
wait for 20 ns;
get_controller_status(stat_2, ID_2, mem_bus(2));
check(stat_2.receiver, "Node 2 lost arbitration!");
read_alc(alc, ID_2, mem_bus(2));
check(alc = 12, "Arbitration lost at correct bit by Node 2!");
......
......@@ -213,11 +213,21 @@ package body btr_fd_feature is
CAN_generate_frame(rand_ctr, CAN_frame_1);
CAN_frame_1.brs := BR_SHIFT;
CAN_frame_1.frame_format := FD_CAN;
-- Force DLC length to 1 byte only not to have long test run time!
CAN_frame_1.dlc := "0001";
decode_dlc(CAN_frame_1.dlc, CAN_frame_1.data_length);
CAN_frame_1.data(0) := x"AA";
-- We need to make sure that frame is not RTR frame, because CAN FD
-- frames have no RTR frames! This would lead to fail in check between
-- TX and RX frame! Also, we have to re-calculate RWCNT for the check
-- accordingly!
CAN_frame_1.rtr := NO_RTR_FRAME;
decode_dlc_rx_buff(CAN_frame_1.dlc, CAN_frame_1.rwcnt);
-- These data bytes are preloaded to have all elements of memory word
-- defined!
CAN_frame_1.data(1) := x"BB";
CAN_frame_1.data(2) := x"CC";
CAN_frame_1.data(3) := x"DD";
......
......@@ -139,7 +139,10 @@ package body command_rrb_feature is
CAN_generate_frame(rand_ctr, frame_1);
CAN_insert_TX_frame(frame_1, 1, ID_2, mem_bus(2));
send_TXT_buf_cmd(buf_set_ready, 1, ID_2, mem_bus(2));
CAN_wait_frame_sent(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
get_rx_buf_state(rx_buf_info, ID_1, mem_bus(1));
check(rx_buf_info.rx_write_pointer /= 0, "Write pointer not 0");
......@@ -180,6 +183,9 @@ package body command_rrb_feature is
check_false(rx_buf_info.rx_empty, "Empty flag not set");
check(rx_buf_info.rx_frame_count = 1, "Frame count 1");
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
-----------------------------------------------------------------------
-- 4. Send frame by Node 2. Wait until Node 1 starts receiving. Wait
-- for random amount of time and issue COMMAND[RRB]. Wait until
......@@ -189,8 +195,6 @@ package body command_rrb_feature is
-----------------------------------------------------------------------
info("Step 4");
CAN_generate_frame(rand_ctr, frame_1);
-- To avoid long runs have only shorter frames!
frame_1.data_length := frame_1.data_length mod 9;
CAN_insert_TX_frame(frame_1, 1, ID_2, mem_bus(2));
send_TXT_buf_cmd(buf_set_ready, 1, ID_2, mem_bus(2));
......@@ -200,6 +204,7 @@ package body command_rrb_feature is
command.release_rec_buffer := true;
give_controller_command(command, ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(2));
get_rx_buf_state(rx_buf_info, ID_1, mem_bus(1));
......@@ -223,12 +228,12 @@ package body command_rrb_feature is
-----------------------------------------------------------------------
info("Step 5");
CAN_generate_frame(rand_ctr, frame_1);
-- To avoid long runs have only shorter frames!
frame_1.data_length := frame_1.data_length mod 9;
CAN_insert_TX_frame(frame_1, 1, ID_2, mem_bus(2));
send_TXT_buf_cmd(buf_set_ready, 1, ID_2, mem_bus(2));
CAN_wait_frame_sent(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
get_rx_buf_state(rx_buf_info, ID_1, mem_bus(1));
check(rx_buf_info.rx_write_pointer /= 0, "Write pointer not 0");
......@@ -238,6 +243,10 @@ package body command_rrb_feature is
CAN_read_frame(frame_rx, ID_1, mem_bus(1));
CAN_compare_frames(frame_rx, frame_1, false, frames_equal);
info("TX frame:");
CAN_print_frame(frame_1);
info("RX frame:");
CAN_print_frame(frame_rx);
check(frames_equal, "TX vs. RX frames match!");
-- Issue COMMAND[RRB] to clean-up after itself (for next iterations)
......
......@@ -193,9 +193,19 @@ package body error_rules_a_feature is
wait for 20 ns;
release_bus_level(so.bl_force);
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
wait for 20 ns; -- To update error counters!
-- We need to check right away, not when node becomes idle! The reason
-- is:
-- When forcing recessive, Node 2 is already in Error delimiter and
-- it will therefore finish its error delimiter and go idle during the
-- time of Active error flag of Node 1 which we force Recessive.
-- So at time when we release the bus and Node 1 finally transmitts its
-- Active Error flag, Node 2 will already accept this as SOF, detect
-- Stuff Error and will transmitt error frame! Due to this Node 1 will
-- increment its REC by 8 because it detected Dominant bit after sending
-- Active Error flag. So when we would wait until idle, REC of Node 1
-- would be higher by 8 due to that detected dominant bit!
read_error_counters(err_counters_3, ID_1, mem_bus(1));
check(err_counters_2.rx_counter + 129 = err_counters_3.rx_counter,
"RX counter incremented by 8 for each recessive during error flag! " &
......@@ -204,6 +214,9 @@ package body error_rules_a_feature is
check(err_counters_2.tx_counter = err_counters_3.tx_counter,
"TX counter unchanged in Receiver!");
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
return;
end procedure;
......
......@@ -106,11 +106,15 @@ package body stuff_in_data_feature is
info("Step 1");
CAN_generate_frame(rand_ctr, CAN_frame);
-- Use only DLC of 1, as data byte 1 is set so that stuff bit is
-- inserted at last bit of data field!
CAN_frame.dlc := "0001";
CAN_frame.data(0) := x"21";
CAN_frame.rtr := NO_RTR_FRAME;
CAN_frame.frame_format := FD_CAN;
decode_dlc(CAN_frame.dlc, CAN_frame.data_length);
CAN_frame.data(0) := x"21";
decode_dlc_rx_buff(CAN_frame.dlc, CAN_frame.rwcnt);
CAN_send_frame(CAN_frame, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_frame_sent(ID_1, mem_bus(1));
......
......@@ -240,8 +240,24 @@ package body trv_delay_feature is
if (rand_time = 0) then
rand_time := 1;
end if;
-----------------------------------------------------------------------
-- Here we avoid explicit multiples of 10 ns! The reason is following:
-- When delay is e.g. 120 ns, then value will arrive at CAN RX when
-- rising_edge is active. Therefore sampled value might, or might not
-- be processed by clock based on which delta cycle was processed
-- first (Since signal delayer does not work with system clocks, it
-- might not be processed the same way as e.g. shift register!)
-- This would cause occasional test failures based on which process
-- was executed first (either rising_edge sampling the data, or data
-- delayed by signal delayer).
-----------------------------------------------------------------------
if (rand_time mod 10 = 0) then
rand_time := rand_time + 1;
end if;
ftr_tb_set_tran_delay(rand_time * 1 ns, ID_1, so.ftr_tb_trv_delay);
info("Random time is: " & integer'image(rand_time) & " ns");
ftr_tb_set_tran_delay((rand_time * 1 ns), ID_1, so.ftr_tb_trv_delay);
CAN_send_frame(CAN_TX_frame, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_frame_sent(ID_2, mem_bus(2));
......
......@@ -3465,12 +3465,16 @@ package body CANtestLib is
outcome := true;
if (frame_A.frame_format /= frame_B.frame_format) then
info("Frame format (FDF) mismatch");
info("Frame format (FDF) mismatch A: " &
std_logic'image(frame_A.frame_format) & " B: " &
std_logic'image(frame_B.frame_format));
outcome := false;
end if;
if (frame_A.ident_type /= frame_B.ident_type) then
info("Identifier type (IDE) mismatch");
info("Identifier type (IDE) mismatch A: " &
std_logic'image(frame_A.ident_type) & " B: " &
std_logic'image(frame_B.ident_type));
outcome := false;
end if;
......@@ -3486,25 +3490,32 @@ package body CANtestLib is
-- BRS bit is compared only in FD frame
if (frame_A.frame_format = FD_CAN) then
if (frame_A.brs /= frame_B.brs) then
info("Bit-rate shift (BRS) mismatch");
info("Bit-rate shift (BRS) mismatch A: " &
std_logic'image(frame_A.brs) & " B: " &
std_logic'image(frame_B.brs));
outcome := false;
end if;
end if;
-- Received word count
if (frame_A.rwcnt /= frame_B.rwcnt) then
info("Read word count (RWCNT) mismatch");
info("Read word count (RWCNT) mismatch A: " &
integer'image(frame_A.rwcnt) & " B: " &
integer'image(frame_B.rwcnt));
outcome := false;
end if;
-- DLC comparison
if (frame_A.dlc /= frame_B.dlc) then
info("Data length code (DLC) mismatch");
info("Data length code (DLC) mismatch A: " &
to_hstring(frame_A.dlc) & " B: " &
to_hstring(frame_B.dlc));
outcome := false;
end if;
if (frame_A.identifier /= frame_B.identifier) then
info("Identifier mismatch");
info("Identifier mismatch A: " & integer'image(frame_A.identifier) &
" B: " & integer'image(frame_B.identifier));
outcome := false;
end if;
......
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