Commit 3f0b30de authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Split register list into stand-alone package.

Furthermore, move declaration of "t_memory_reg" into
separate package so that they are not declared twice
when multiple memory maps are generated.
parent 9e3d4843
......@@ -4,4 +4,9 @@ d="$(dirname "$0")"
# Note: the script uses relative paths and must be called from this directory
cd "$d"
python3 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --updVHDLPackage True --updHeaderFile True --updLyxDocs True --updRTLRegMap True
python3 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml \
--updVHDLPackage True \
--updHeaderFile True \
--updLyxDocs True \
--updRTLRegMap True \
--updTbPackage True
......@@ -38,6 +38,7 @@ from pyXact_generator.gen_lib import *
from pyXact_generator.HeaderAddrGeneratorWrapper import HeaderAddrGeneratorWrapper
from pyXact_generator.LyxAddrGeneratorWrapper import LyxAddrGeneratorWrapper
from pyXact_generator.VhdlAddrGeneratorWrapper import VhdlAddrGeneratorWrapper
from pyXact_generator.VhdlTbAddrGeneratorWrapper import VhdlTbAddrGeneratorWrapper
from pyXact_generator.VhdlRegMapGeneratorWrapper import VhdlRegMapGeneratorWrapper
MIT_LICENSE_PATH = "../LICENSE"
......@@ -67,6 +68,11 @@ def parse_args():
parser.add_argument('--updRTLRegMap', dest='updRTLRegMap', help="""Whether VHDL
RTL register map should be generated.
(../src/Registers_Memory_Interface/generated)""")
parser.add_argument('--updTbPackage', dest='updTbPackage', help="""Whether Testbench
package with register list should be generated
(../test/lib)""")
return parser.parse_args();
......@@ -138,6 +144,23 @@ def ctu_can_update_vhdl_rtl(specPath, licensePath, memMap, wordWidthBit, outDir)
vhdlRTLGeneratorWrapper.do_update()
def ctu_can_update_vhdl_tb_package(specPath, licensePath, memMap,
wordWidthBit, outPath, packName):
"""
Update VHDL Testbench packages of CTU CAN FD register maps.
"""
tbAddrGeneratorWrapper = VhdlTbAddrGeneratorWrapper()
tbAddrGeneratorWrapper.xactSpec = specPath
tbAddrGeneratorWrapper.licPath = licensePath
tbAddrGeneratorWrapper.memMap = memMap
tbAddrGeneratorWrapper.wordWidth = wordWidthBit
tbAddrGeneratorWrapper.outFile = outPath
tbAddrGeneratorWrapper.packName = packName
tbAddrGeneratorWrapper.do_update()
if __name__ == '__main__':
args = parse_args()
print( 80 * "*")
......@@ -227,7 +250,7 @@ if __name__ == '__main__':
###########################################################################
# Generate VHDL RTL codes
###########################################################################
###########################################################################
if (str_arg_to_bool(args.updRTLRegMap)):
print("Generating CAN FD memory registers Documentation...\n")
......@@ -242,7 +265,24 @@ if __name__ == '__main__':
# visualisaion only
print("\nDone\n")
###########################################################################
# Generate Testbench package
###########################################################################
if (str_arg_to_bool(args.updTbPackage)):
print("Generating Testbench package...\n")
ctu_can_update_vhdl_tb_package(specPath=args.xactSpec,
licensePath=MIT_LICENSE_PATH,
memMap="CAN_Registers",
wordWidthBit=32,
outPath="../test/lib/can_fd_tb_register_map.vhd",
packName="can_fd_tb_register_map")
print("\nDone\n")
print( 80 * "*")
print("** Finished")
print(80 * "*")
......
......@@ -49,26 +49,6 @@ use ieee.std_logic_1164.all;
package can_fd_frame_format is
------------------------------------------------------------------------------
-- Common types
------------------------------------------------------------------------------
type t_reg_type is (
reg_none,
reg_write_only,
reg_read_only,
reg_read_write,
reg_read_write_once
);
type t_memory_reg is record
address : std_logic_vector(11 downto 0);
size : integer;
reg_type : t_reg_type;
reset_val : std_logic_vector(31 downto 0);
is_implem : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Address block: CAN_FD_Frame_format
......@@ -84,51 +64,6 @@ package can_fd_frame_format is
constant DATA_5_8_W_ADR : std_logic_vector(11 downto 0) := x"014";
constant DATA_61_64_W_ADR : std_logic_vector(11 downto 0) := x"04C";
------------------------------------------------------------------------------
-- Register list
------------------------------------------------------------------------------
type t_CAN_FD_Frame_format_list is array (0 to 6) of t_memory_reg;
constant CAN_FD_Frame_format_list : t_CAN_FD_Frame_format_list :=(
(address => FRAME_FORM_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "00000000000000001111111011101111"),
(address => IDENTIFIER_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "00011111111111111111111111111111"),
(address => TIMESTAMP_L_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => TIMESTAMP_U_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_1_4_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_5_8_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111"),
(address => DATA_61_64_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000",
is_implem => "11111111111111111111111111111111")
);
------------------------------------------------------------------------------
-- FRAME_FORM_W register
--
......
This diff is collapsed.
......@@ -81,6 +81,8 @@ use lib.cmn_lib.all;
use lib.drv_stat_pkg.all;
use lib.reduce_lib.all;
use lib.can_config.all;
use lib.tb_reg_map_defs_pkg.All;
use lib.can_fd_tb_register_map.All;
use lib.CAN_FD_register_map.all;
......
......@@ -87,6 +87,7 @@ USE work.randomLib.All;
use work.can_constants.all;
use work.drv_stat_pkg.all;
use work.can_config.all;
use work.tb_reg_map_defs_pkg.All;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
......
This diff is collapsed.
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Package with types used by register map generator generated packages for TB.
--
--------------------------------------------------------------------------------
-- Revision History:
-- 17.01.2020 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
package tb_reg_map_defs_pkg is
------------------------------------------------------------------------------
-- Common types
------------------------------------------------------------------------------
type t_reg_type is (
reg_none,
reg_write_only,
reg_read_only,
reg_read_write,
reg_read_write_once
);
type t_memory_reg is record
address : std_logic_vector(11 downto 0);
size : integer;
reg_type : t_reg_type;
reset_val : std_logic_vector(31 downto 0);
is_implem : std_logic_vector(31 downto 0);
end record;
end package;
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