Commit 3d788a14 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Remove prescaler unit test since it apparently modeled prescaler behavior wrong!!

parent 68756170
Pipeline #20210 failed with stages
in 3 minutes and 19 seconds
......@@ -25,8 +25,6 @@ unit:
wave: unit/Int_Manager/intm_unit.tcl
mess_filt:
wave: unit/Message_filter/msft_unit.tcl
presc:
wave: unit/Prescaler/prsc_unit.tcl
protocol_control:
wave: unit/Protocol_Control/pctl_unit.tcl
iterations: 100
......
This diff is collapsed.
*-27.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@200
-Test details
@22
top.tb_presc_unit_test.tb.i_test.iterations
top.tb_presc_unit_test.tb.i_test.log_level
top.tb_presc_unit_test.tb.i_test.error_beh
top.tb_presc_unit_test.tb.i_test.loop_ctr
@200
-System
@22
top.tb_presc_unit_test.tb.i_test.res_n
top.tb_presc_unit_test.tb.i_test.clk_sys
@200
-DUT inputs (generated)
@800200
-Bit time settings
@24
+{Time quanta (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_tq_nbt[7:0]
+{PROP_SEG (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_prs_nbt[6:0]
+{PH1_SEG (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_ph1_nbt[5:0]
+{PH2_SEG (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_ph2_nbt[5:0]
+{Synchron. jump width (Nominal)} top.tb_presc_unit_test.tb.i_test.drv_sjw_nbt[4:0]
+{Time quanta (Data)} top.tb_presc_unit_test.tb.i_test.drv_tq_dbt[7:0]
+{PROP_SEG (Data)} top.tb_presc_unit_test.tb.i_test.drv_prs_dbt[5:0]
+{PH1_SEG (Data)} top.tb_presc_unit_test.tb.i_test.drv_ph1_dbt[4:0]
+{PH2_SEG (Data)} top.tb_presc_unit_test.tb.i_test.drv_ph2_dbt[4:0]
+{Synchron. jump width (Data)} top.tb_presc_unit_test.tb.i_test.drv_sjw_dbt[4:0]
@1000200
-Bit time settings
@22
+{Synchronization edge} top.tb_presc_unit_test.tb.i_test.sync_edge
@24
+{Sample control} top.tb_presc_unit_test.tb.i_test.sp_control[1:0]
+{Synchronization control} top.tb_presc_unit_test.tb.i_test.sync_control[1:0]
@200
-DUT outputs
@800200
-Triggerring signals
@22
+{SYNC (Nominal)} top.tb_presc_unit_test.tb.i_test.sync_nbt
+{SYNC del.1 (Nominal)} top.tb_presc_unit_test.tb.i_test.sync_nbt_del_1
+{SAMPLE (Nominal)} top.tb_presc_unit_test.tb.i_test.sample_nbt
+{SAMPLE del.1 (Nominal)} top.tb_presc_unit_test.tb.i_test.sample_nbt_del_1
+{SAMPLE del.2 (Nominal)} top.tb_presc_unit_test.tb.i_test.sample_nbt_del_2
+{SYNC (Data)} top.tb_presc_unit_test.tb.i_test.sync_dbt
+{SYNC del.1 (Data)} top.tb_presc_unit_test.tb.i_test.sync_dbt_del_1
+{SAMPLE (Data)} top.tb_presc_unit_test.tb.i_test.sample_dbt
+{SAMPLE del.1 (Data)} top.tb_presc_unit_test.tb.i_test.sample_dbt_del_1
+{SAMPLE del.2 (Data)} top.tb_presc_unit_test.tb.i_test.sample_dbt_del_2
@1000200
-Triggerring signals
@22
+{Bit time state} top.tb_presc_unit_test.tb.i_test.bt_fsm_out
+{Hard sync appeared} top.tb_presc_unit_test.tb.i_test.hard_sync_edge_valid
@200
-Testbench internals
@24
+{Expected bit time with resync} top.tb_presc_unit_test.tb.i_test.resync_bit_time_length
@200
-Error counters
@24
+{Inform. proc. time corrupted} top.tb_presc_unit_test.tb.i_test.ipt_err_ctr
+{Coherency checks failed} top.tb_presc_unit_test.tb.i_test.coh_err_ctr
+{Sync signal missed} top.tb_presc_unit_test.tb.i_test.sync_seq_err_ctr
+{Sample signal missed} top.tb_presc_unit_test.tb.i_test.sample_seq_err_ctr
@200
-Internal DUT signals
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
##
## Project advisor: Jiri Novak <jnovak@fel.cvut.cz>
## Department of Measurement (http://meas.fel.cvut.cz/)
## Faculty of Electrical Engineering (http://www.fel.cvut.cz)
## Czech Technical University (http://www.cvut.cz/)
##
## Permission is hereby granted, free of charge, to any person obtaining a copy
## of this VHDL component and associated documentation files (the "Component"),
## to deal in the Component without restriction, including without limitation
## the rights to use, copy, modify, merge, publish, distribute, sublicense,
## and/or sell copies of the Component, and to permit persons to whom the
## Component is furnished to do so, subject to the following conditions:
##
## The above copyright notice and this permission notice shall be included in
## all copies or substantial portions of the Component.
##
## THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
## AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
## FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
## IN THE COMPONENT.
##
## The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
## Anybody who wants to implement this IP core on silicon has to obtain a CAN
## protocol license from Bosch.
##
################################################################################
################################################################################
## Description:
## Prescaler unit test handling script
################################################################################
global TCOMP
start_CAN_simulation "presc_unit_test_wrapper"
################################################################################
# Adding the waves
################################################################################
#Add common waves for each test entity
add_test_status_waves
add_system_waves
#Add circuit specific signals
add wave -noupdate -divider -height 20 "DUT inputs (generated)"
add wave -group "Bit time settings" \
-label "Time quanta (Nominal)" -unsigned $TCOMP/drv_tq_nbt \
-label "PROP_SEG (Nominal)" -unsigned $TCOMP/drv_prs_nbt \
-label "PH1_SEG (Nominal)" -unsigned $TCOMP/drv_ph1_nbt \
-label "PH2_SEG (Nominal)" -unsigned $TCOMP/drv_ph2_nbt \
-label "Synchron. jump width (Nominal)" -unsigned $TCOMP/drv_sjw_nbt \
-label "Time quanta (Data)" -unsigned $TCOMP/drv_tq_dbt \
-label "PROP_SEG (Data)" -unsigned $TCOMP/drv_prs_dbt \
-label "PH1_SEG (Data)" -unsigned $TCOMP/drv_ph1_dbt \
-label "PH2_SEG (Data)" -unsigned $TCOMP/drv_ph2_dbt \
-label "Synchron. jump width (Data)" -unsigned $TCOMP/drv_sjw_dbt
add wave -label "Synchronization edge" $TCOMP/sync_edge
add wave -label "Sample control" -unsigned $TCOMP/sp_control
add wave -label "Synchronization control" -unsigned $TCOMP/sync_control
add wave -noupdate -divider -height 20 "DUT outputs"
add wave -group "Triggerring signals" \
-label "SYNC (Nominal)" $TCOMP/sync_nbt \
-label "SYNC del.1 (Nominal)" $TCOMP/sync_nbt_del_1 \
-label "SAMPLE (Nominal)" $TCOMP/sample_nbt \
-label "SAMPLE del.1 (Nominal)" $TCOMP/sample_nbt_del_1 \
-label "SAMPLE del.2 (Nominal)" $TCOMP/sample_nbt_del_2 \
-label "SYNC (Data)" $TCOMP/sync_dbt \
-label "SYNC del.1 (Data)" $TCOMP/sync_dbt_del_1 \
-label "SAMPLE (Data)" $TCOMP/sample_dbt \
-label "SAMPLE del.1 (Data)" $TCOMP/sample_dbt_del_1 \
-label "SAMPLE del.2 (Data)" $TCOMP/sample_dbt_del_2
add wave -label "Bit time state" $TCOMP/bt_fsm_out
add wave -label "Hard sync appeared" $TCOMP/hard_sync_edge_valid
add wave -noupdate -divider -height 20 "Testbench internals"
add wave -label "Expected bit time with resync" -unsigned $TCOMP/resync_bit_time_length
add wave -noupdate -divider -height 20 "Error counters"
add wave -label "Inform. proc. time corrupted" \
-unsigned $TCOMP/ipt_err_ctr
add wave -label "Coherency checks failed" -unsigned $TCOMP/coh_err_ctr
add wave -label "Sync signal missed" -unsigned $TCOMP/sync_seq_err_ctr
add wave -label "Sample signal missed" -unsigned $TCOMP/sample_seq_err_ctr
add wave -noupdate -divider -height 20 "Internal DUT signals"
add wave -label "FSM preset" $TCOMP/prescaler_comp/fsm_preset
add wave -label "Time quantum start" $TCOMP/prescaler_comp/tq_edge
add wave -label "Bit time counter" -unsigned $TCOMP/prescaler_comp/bt_counter
add wave -label "PH1 (after sync.)" -unsigned $TCOMP/prescaler_comp/ph1_real
add wave -label "PH2 (after sync.)" -unsigned $TCOMP/prescaler_comp/ph2_real
################################################################################
# Execute the simulation, gather results
################################################################################
run_simulation
get_test_results
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