Commit 3cabcd13 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Swapped priority of set/reset for DOI interrupt. Added

constant with definition of Interrupt Set/Clear priorities.
parent 1fe7eabc
......@@ -5397,40 +5397,40 @@ Reset value\end_layout
 
\end_layout
\begin_layout Description
RXI Frame Received interrupt.
RXI Frame Received interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
TXI Frame Transmitted sucesfully interrupt.
TXI Frame Transmitted sucesfully interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
EWLI Error warning limit reached interrupt.
EWLI Error warning limit reached interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
DOI Data overrun on RX Buffer Interrupt.
DOI Data overrun on RX Buffer Interrupt. Interrupt clear has priority over set.
\end_layout
\begin_layout Description
EPI Node became error passive or bus off interrupt.
EPI Node became error passive or bus off interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
ALI Arbitration lost Interrupt.
ALI Arbitration lost Interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
BEI Bus Error interrupt.
BEI Bus Error interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
LFI Event logging finished interrupt.
LFI Event logging finished interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
RXFI Receive Buffer full interrupt.
RXFI Receive Buffer full interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
BSI Bit-rate shifted interrupt.
BSI Bit-rate shifted interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
RBNEI Receive Buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt.
RBNEI Receive Buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt. Interrupt set has priority over clear.
\end_layout
\begin_layout Description
TXBHCI TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core which changes TXT Buffer state to TX Ok, Error or Aborted, this interrupt will be acivated.
TXBHCI TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core which changes TXT Buffer state to TX Ok, Error or Aborted, this interrupt will be acivated. Interrupt set has priority over clear.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
......
......@@ -583,7 +583,7 @@
<ipxact:field>
<ipxact:name>RXI</ipxact:name>
<ipxact:displayName>RXI</ipxact:displayName>
<ipxact:description>Frame Received interrupt.</ipxact:description>
<ipxact:description>Frame Received interrupt. Interrupt set has priority over clear. </ipxact:description>
<ipxact:bitOffset>0</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -596,7 +596,7 @@
<ipxact:field>
<ipxact:name>TXI</ipxact:name>
<ipxact:displayName>TXI</ipxact:displayName>
<ipxact:description>Frame Transmitted sucesfully interrupt.</ipxact:description>
<ipxact:description>Frame Transmitted sucesfully interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>1</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -609,7 +609,7 @@
<ipxact:field>
<ipxact:name>EWLI</ipxact:name>
<ipxact:displayName>EWLI</ipxact:displayName>
<ipxact:description>Error warning limit reached interrupt.</ipxact:description>
<ipxact:description>Error warning limit reached interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>2</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -622,7 +622,7 @@
<ipxact:field>
<ipxact:name>DOI</ipxact:name>
<ipxact:displayName>DOI</ipxact:displayName>
<ipxact:description>Data overrun on RX Buffer Interrupt.</ipxact:description>
<ipxact:description>Data overrun on RX Buffer Interrupt. Interrupt clear has priority over set.</ipxact:description>
<ipxact:bitOffset>3</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -635,7 +635,7 @@
<ipxact:field>
<ipxact:name>EPI</ipxact:name>
<ipxact:displayName>EPI</ipxact:displayName>
<ipxact:description>Node became error passive or bus off interrupt.</ipxact:description>
<ipxact:description>Node became error passive or bus off interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>4</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -648,7 +648,7 @@
<ipxact:field>
<ipxact:name>ALI</ipxact:name>
<ipxact:displayName>ALI</ipxact:displayName>
<ipxact:description>Arbitration lost Interrupt.</ipxact:description>
<ipxact:description>Arbitration lost Interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>5</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -661,7 +661,7 @@
<ipxact:field>
<ipxact:name>BEI</ipxact:name>
<ipxact:displayName>BEI</ipxact:displayName>
<ipxact:description>Bus Error interrupt.</ipxact:description>
<ipxact:description>Bus Error interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>6</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -674,7 +674,7 @@
<ipxact:field>
<ipxact:name>LFI</ipxact:name>
<ipxact:displayName>LFI</ipxact:displayName>
<ipxact:description>Event logging finished interrupt.</ipxact:description>
<ipxact:description>Event logging finished interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>7</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -687,7 +687,7 @@
<ipxact:field>
<ipxact:name>RXFI</ipxact:name>
<ipxact:displayName>RXFI</ipxact:displayName>
<ipxact:description>Receive Buffer full interrupt.</ipxact:description>
<ipxact:description>Receive Buffer full interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>8</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -700,7 +700,7 @@
<ipxact:field>
<ipxact:name>BSI</ipxact:name>
<ipxact:displayName>BSI</ipxact:displayName>
<ipxact:description>Bit-rate shifted interrupt.</ipxact:description>
<ipxact:description>Bit-rate shifted interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>9</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -713,7 +713,7 @@
<ipxact:field>
<ipxact:name>RBNEI</ipxact:name>
<ipxact:displayName>RBNEI</ipxact:displayName>
<ipxact:description>Receive Buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt.</ipxact:description>
<ipxact:description>Receive Buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>10</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......@@ -726,7 +726,7 @@
<ipxact:field>
<ipxact:name>TXBHCI</ipxact:name>
<ipxact:displayName>TXBHCI</ipxact:displayName>
<ipxact:description>TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core which changes TXT Buffer state to TX Ok, Error or Aborted, this interrupt will be acivated.</ipxact:description>
<ipxact:description>TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core which changes TXT Buffer state to TX Ok, Error or Aborted, this interrupt will be acivated. Interrupt set has priority over clear.</ipxact:description>
<ipxact:bitOffset>11</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
......
......@@ -194,6 +194,26 @@ architecture rtl of int_manager is
constant zero_mask : std_logic_vector(int_count - 1 downto 0)
:= (OTHERS => '0');
----------------------------------------------------------------------------
-- Reset over set priority assignment
----------------------------------------------------------------------------
type int_s_r_priority_type is array(0 to int_count - 1) of boolean;
constant int_clear_priority : int_s_r_priority_type :=
(false, -- RXI_IND
false, -- TXI_IND
false, -- EWLI_IND
true, -- DOI_IND
false, -- EPI_IND
false, -- ALI_IND
false, -- BEI_IND
false, -- LFI_IND
false, -- RXFI_IND
false, -- BSI_IND
false, -- RBNEI_IND
false -- TXBHCI_IND
);
begin
-- Driving bus aliases
......@@ -222,13 +242,13 @@ begin
---------------------------------------------------------------------------
-- Interrupt register masking and enabling
---------------------------------------------------------------------------
int_input_active(BEI_IND) <= error_valid;
int_input_active(ALI_IND) <= arbitration_lost;
int_input_active(EPI_IND) <= error_passive_changed;
int_input_active(DOI_IND) <= rx_message_disc;
int_input_active(EWLI_IND) <= error_warning_limit;
int_input_active(TXI_IND) <= tx_finished;
int_input_active(RXI_IND) <= rec_message_valid;
int_input_active(TXI_IND) <= tx_finished;
int_input_active(EWLI_IND) <= error_warning_limit;
int_input_active(DOI_IND) <= rx_message_disc;
int_input_active(EPI_IND) <= error_passive_changed;
int_input_active(ALI_IND) <= arbitration_lost;
int_input_active(BEI_IND) <= error_valid;
int_input_active(LFI_IND) <= loger_finished;
int_input_active(RXFI_IND) <= rx_full;
int_input_active(BSI_IND) <= br_shifted;
......@@ -244,7 +264,7 @@ begin
int_module_comp : int_module
generic map(
reset_polarity => ACT_RESET,
clear_priority => false
clear_priority => int_clear_priority(i)
)
port map(
clk_sys => clk_sys,
......
......@@ -445,12 +445,24 @@ begin
int_mask_exp(i) <= '0';
end if;
-------------------------------------------------------------------
-- Interrupt clear and capturing!
-- Clear priority only for DOI, for others set priority.
-------------------------------------------------------------------
if (i = DOI_IND) then
if (drv_int_clear(i) = '1') then
int_status_exp(i) <= '0';
elsif (int_input(i) = '1' and int_mask_exp(i) = '0') then
int_status_exp(i) <= '1';
end if;
else
if (int_input(i) = '1' and int_mask_exp(i) = '0') then
int_status_exp(i) <= '1';
elsif (drv_int_clear(i) = '1') then
int_status_exp(i) <= '0';
end if;
end if;
end loop;
-- Calculating expected interrupt output
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment