Commit 3af98111 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '156-tx_arb_unit_test-fails-on-205th-iteration' into 'master'

Resolve "tx_arb_unit_test fails on 205th iteration"

Closes #156

See merge request illeondr/CAN_FD_IP_Core!148
parents f2bd8951 b491690d
Pipeline #2028 failed with stages
in 24 minutes and 27 seconds
......@@ -43,6 +43,8 @@
-- 30.5.2016 Created file
-- 23.4.2018 Updated test to cover TX Arbitrator with continous timestamp
-- load.
-- 5.9.2018 Relaxed timing conditions. Allowed one clock cycle mismatch
-- between DUT and model.
--------------------------------------------------------------------------------
Library ieee;
......@@ -140,6 +142,13 @@ architecture tx_arb_unit_test of CAN_test is
-- Delay propagation of metadata to the output!
signal del_counter : natural;
-- Signals indicating mismatch between Model and DUT
signal frame_valid_mism : boolean;
signal metadata_mism : boolean;
signal hw_cmd_buf_index_mism : boolean;
signal sel_buf_mism : boolean;
signal mism_ctr : natural := 0;
----------------------------------------------------------------------------
-- Compare function for two 64 bit std logic vectors
----------------------------------------------------------------------------
......@@ -228,12 +237,6 @@ begin
apply_rand_seed(seed, 3, rand_ctr_1);
end if;
------------------------------------------------------------------------
-- Additional delay to be sure that we catch HW command lock as real
-- TX Arbitrator does by combinational path!
------------------------------------------------------------------------
wait for 1 ns;
-- Choose random TXT Buffer
rand_real_v(rand_ctr_1, buf_index);
buf_index := buf_index * 3.0;
......@@ -531,40 +534,46 @@ begin
----------------------------------------------------------------------------
-- Compare DUT outputs with model outputs
----------------------------------------------------------------------------
cmp_proc : process
begin
frame_valid_mism <= true when (mod_frame_valid_out /= tran_frame_valid_out)
else
false;
if (mod_frame_valid_out /= tran_frame_valid_out and now /= 0 fs) then
-- LCOV_EXCL_START
log("DUT and Model Frame valid not matching!", error_l, log_level);
cmp_err_ctr <= cmp_err_ctr + 1;
-- LCOV_EXCL_STOP
end if;
metadata_mism <= true when
((mod_dlc_out /= tran_dlc_out) or
(mod_is_rtr /= tran_is_rtr) or
(mod_ident_type_out /= tran_ident_type_out) or
(mod_frame_type_out /= tran_frame_type_out))
else
false;
hw_cmd_buf_index_mism <= true when (txt_hw_cmd_buf_index /= mod_buf_index)
else
false;
sel_buf_mism <= true when (last_locked_index /= mod_buf_index and
txtb_changed = '0')
else
false;
if (((mod_dlc_out /= tran_dlc_out) or
(mod_is_rtr /= tran_is_rtr) or
(mod_ident_type_out /= tran_ident_type_out) or
(mod_frame_type_out /= tran_frame_type_out)) and now /= 0 fs)
then
-- LCOV_EXCL_START
log("DUT and Model metadata not matching!", error_l, log_level);
cmp_err_ctr <= cmp_err_ctr + 1;
-- LCOV_EXCL_STOP
end if;
if (txt_hw_cmd_buf_index /= mod_buf_index and now /= 0 fs)
----------------------------------------------------------------------------
-- Allow only one clock cycle mismatch!
----------------------------------------------------------------------------
cons_check_proc : process
begin
if (frame_valid_mism or metadata_mism or sel_buf_mism or
hw_cmd_buf_index_mism)
then
-- LCOV_EXCL_START
log("DUT and Model buffer index not matching!", error_l, log_level);
cmp_err_ctr <= cmp_err_ctr + 1;
-- LCOV_EXCL_STOP
mism_ctr <= mism_ctr + 1;
else
mism_ctr <= 0;
end if;
if (last_locked_index /= mod_buf_index and
txtb_changed = '0' and now /= 0 fs)
then
wait for 0 ns;
if (mism_ctr = 2) then
-- LCOV_EXCL_START
log("Buffer change not detected!", error_l, log_level);
log("Mismatch for more than 2 clock cycles!", error_l, log_level);
cmp_err_ctr <= cmp_err_ctr + 1;
-- LCOV_EXCL_STOP
end if;
......
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