Commit 39f4a898 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '194-protocol-control-rework' into 'master'

Resolve "Protocol Control rework"

Closes #194

See merge request !247
parents 2d7a3e50 4ae4f4a9
Pipeline #9587 canceled with stages
in 15 seconds
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{signal: [
{name: 'CAN frame field', wave: '53..........45', data: ['SOF', 'Base Identifier', 'SRR', 'IDE'], node: '.......'},
{name: 'Control counter value', wave: 'x===========x.', data: ['10', '9','8','7','6','5','4','3','2','1','0'], node: '.......'},
],
//edge:['a<->b', 'c<->d', 'e~>f Destuff', 'f~>g Process', 'g~>i Stuff'],
}
{signal: [
{name: 'System clock', wave: '10101010|l1010101',
node: '....a...|...c....'},
{name: 'CAN Bus bit', wave: '3.......4........', data: ['Bit N', 'Bit N + 1'],
node: '........|........'},
{name: 'Pipeline stage', wave: 'x.2.2.x.|.2.2.x..', data: ['Destuff', 'Process', 'Destuff', 'Process'],
node: '........|........'},
{name: 'Destuffed bit', wave: '0.......|...1....', data:['']},
{name: 'CRC15', wave: '3.....4.|........', data:['Bit N - 1', 'Bit N']},
{name: 'CRC15 trigger', wave: '0...1.0.|........', data:['']},
{name: 'CRC17 / CRC21', wave: '3.....4.|.....5..', data:['Bit N - 1', 'Bit N', 'Bit N + 1']},
{name: 'CRC17 / CRC21 trigger', wave: '0...1.0.|...1.0..', data:[''],
node: '....b.......d....'},
],
foot: {text:
['tspan', 'Sample point of Bit N Sample point of Bit N + 1 (Stuff Bit) '],
},
edge:['a-b','c-d'],
}
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{signal: [
{name: 'CAN frame field', wave: '53..........45', data: ['SOF', 'Base Identifier', 'SRR', 'IDE'], node: '.......'},
{name: 'Control counter value', wave: 'x===========x.', data: ['10', '9','8','7','6','5','4','3','2','1','0'], node: '.......'},
{name: 'Arbitration lost', wave: '0....10.......', data: [''], node: '.......'},
{name: 'ALC[ALC_BIT]', wave: 'x....=........', data: ['6'], node: '.......'},
{name: 'ALC[ALC_ID_FIELD]', wave: 'x....=........', data: ['00'], node: '.......'},
],
//edge:['a<->b', 'c<->d', 'e~>f Destuff', 'f~>g Process', 'g~>i Stuff'],
}
{signal: [
{name: 'CAN frame field', wave: '53..........45', data: ['SOF', 'Base Identifier', 'SRR', 'IDE'], node: '.......'},
{name: 'Control counter value', wave: 'x===========x.', data: ['10', '9','8','7','6','5','4','3','2','1','0'], node: '.......'},
],
//edge:['a<->b', 'c<->d', 'e~>f Destuff', 'f~>g Process', 'g~>i Stuff'],
}
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{signal: [
{name: 'System clock', wave: '1010101010|l101010101',
node: '....a.....|...c......'},
{name: 'CAN Bus field', wave: '5.........|...4......', data: ['End of frame ', 'Active Error Flag'],
node: '..........|..........'},
{name: 'Pipeline stage', wave: 'x.3.4.5.x.|.3.x......', data: ['Destuff', 'Process', 'Process + 1', 'Stuff'],
node: '..........|..........'},
{name: 'Form Error', wave: '0...1.0...|..........',
node: '..........|..........'},
{name: 'Error frame request', wave: '0.....1.0.|..........', data: ['0', '1','127'], phase: -0.0,
node: '..........|..........'},
{name: 'Protocol control FSM', wave: '=.......=.|..........', data:['End of Frame', 'Active Error Flag']},
{name: 'RX Data', wave: '0.........|..........', data:['']},
{name: 'TX Data', wave: '1.........|...0......', data:[''],
node: '....b.........d......'},
],
foot: {text:
['tspan', 'Sample point Start of next bit '],
},
edge:['a-b','c-d'],
}
{signal: [
{name: 'System clock', wave: '10101010|l1010101',
node: '....a...|...c....'},
{name: 'CAN Bus bit', wave: '3...4...|...5....', data: ['Bit N', ' Bit N + 1 Bit N + 1', 'Bit N + 2'],
node: '........|........'},
{name: 'Pipeline stage', wave: 'x.2.2.x.|.2.2.x..', data: ['Stuff', 'Stuff + 1', 'Stuff', 'Stuff + 1'],
node: '........|........'},
{name: 'Data Halt', wave: '0.......|.1......', data:['']},
{name: 'CRC15', wave: '3...4...|........', data:['Bit N', 'Bit N + 1']},
{name: 'CRC15 trigger', wave: '0.1.0...|........', data:['']},
{name: 'CRC17 / CRC21', wave: '3.....4.|.....5..', data:['Bit N', 'Bit N + 1', 'Bit N +2']},
{name: 'CRC17 / CRC21 trigger', wave: '0...1.0.|...1.0..', data:[''],
node: '....b.......d....'},
],
foot: {text:
['tspan', 'Start of bit N + 1 Start of bit N + 2 (Stuff bit) '],
},
edge:['a-b','c-d'],
}
{signal: [
{name: 'System clock', wave: 'p..|...', period: 2},
{name: 'Port A Address', wave: 'x.3.x..|......', data: [1]},
{name: 'Port A Data (write)', wave: 'x.3.x..|......', data: ['AA55AA55']},
{name: 'Port A Write', wave: '0.1.0..|......'},
{name: 'Memory content', wave: 'x...2..|......', data: ['AA55AA55']},
{name: 'Port B Address', wave: 'x......|5.x...', data: [1]},
{name: 'Port B Data (read)', wave: 'x......|..5.x.', data: ['AA55AA55']}
]}
{signal: [
{name: 'System clock', wave: '1010101010|l101010101',
node: '....a.....|...c......'},
{name: 'CAN Bus field', wave: '5.........|...4......', data: ['End of frame ', 'Active Error Flag'],
node: '..........|..........'},
{name: 'Pipeline stage', wave: 'x.3.4.5.x.|.3.x......', data: ['Destuff', 'Process', 'Process + 1', 'Stuff'],
node: '..........|..........'},
{name: 'Form Error', wave: '0...1.0...|..........',
node: '..........|..........'},
{name: 'Error frame request', wave: '0.....1.0.|..........', data: ['0', '1','127'], phase: -0.0,
node: '..........|..........'},
{name: 'Protocol control FSM', wave: '=.......=.|..........', data:['End of Frame', 'Active Error Flag']},
{name: 'RX Data', wave: '0.........|..........', data:['']},
{name: 'TX Data', wave: '1.........|...0......', data:[''],
node: '....b.........d......'},
],
foot: {text:
['tspan', 'Sample point Start of next bit '],
},
edge:['a-b','c-d'],
}
{signal: [
{name: 'System clock', wave: 'p..|...', period: 2},
{name: 'Port A Address', wave: 'x.3.x..|......', data: [1]},
{name: 'Port A Data (write)', wave: 'x.3.x..|......', data: ['AA55AA55']},
{name: 'Port A Write', wave: '0.1.0..|......'},
{name: 'Memory content', wave: 'x...2..|......', data: ['AA55AA55']},
{name: 'Port B Address', wave: 'x......|5.x...', data: [1]},
{name: 'Port B Data (read)', wave: 'x......|..5.x.', data: ['AA55AA55']}
]}
{signal: [
{name: 'CAN Bus', wave: '13..4.1.3..4.1.3..4.1.', data: ['CAN frame', 'Error frame', 'CAN frame', 'Error frame', 'CAN frame', 'Error frame'], node: '.......'},
{name: 'Retransmitt counter', wave: '=...=......=......=...', data: ['0', '1', '2', '0'], node: '.......'},
{name: 'Retransmitt limit', wave: '=.....................', data: ['2'], node: '.......'},
{name: 'Transmission type', wave: 'x=....x.=....x.=....x.', data: ['Initial transmission', 'First re-transmission', 'Second re-transmission'], node: '.......'},
{name: 'Operational state', wave: '=5....=.5....=.5....=.', data: ['Idle', 'Transmitter', 'Idle', 'Transmitter', 'Idle', 'Transmitter', 'Idle'], node: '.......'},
{name: 'TXT Buffer state', wave: '=4..=...4..=...4..=...', data: ['Ready', 'TX in Progress', 'Ready', 'TX in Progress', 'Ready', 'TX in Progress','TX Error'], node: '.......'},
],
//edge:['a<->b', 'c<->d', 'e~>f Destuff', 'f~>g Process', 'g~>i Stuff'],
}
{signal: [
{name: 'System clock', wave: '0...p.........', data: [''],
node: '..............'},
{name: 'External reset', wave: '101...........', data: [''], phase: -0.1,
node: '.ac...........'},
{name: 'Soft reset', wave: '0.........10..', data: [''],
node: '..........eg..'},
{name: 'System reset', wave: '01...0.....10.', data: [''], phase: -0.1,
node: '.b...d.....fh.'},
{name: '', node: '..............'},
],
edge:['a->b Assert', 'c~>d De-assert', 'e~>f Assert', 'g~>h De-assert'],
}
{signal: [
{name: 'CAN Bus', wave: '13..4.1.3...4.1.3....1.', data: ['CAN frame', 'Error frame', 'CAN frame', 'Error frame', 'CAN frame'], node: '.......'},
{name: 'Retransmitt counter', wave: '=...=.......=........=.', data: ['0', '1', '2', '0'], node: '.......'},
{name: 'Retransmitt limit', wave: '=......................', data: ['2'], node: '.......'},
{name: 'Transmission type', wave: 'x=....x.=.....x.=....x.', data: ['Initial transmission', 'First re-transmission', 'Second re-transmission'], node: '.......'},
{name: 'Operational state', wave: '=5....=.5.....=.5....=.', data: ['Idle', 'Transmitter', 'Idle', 'Transmitter', 'Idle', 'Transmitter', 'Idle'], node: '.......'},
{name: 'TXT Buffer state', wave: '=4..=...4...=...4....=.', data: ['Ready', 'TX in Progress', 'Ready', 'TX in Progress', 'Ready', 'TX in Progress','TX OK'], node: '.......'},
],
//edge:['a<->b', 'c<->d', 'e~>f Destuff', 'f~>g Process', 'g~>i Stuff'],
}
{signal: [
{name: 'CAN Bus', wave: '13..4.1.3..4.1.3..4.1.', data: ['CAN frame', 'Error frame', 'CAN frame', 'Error frame', 'CAN frame', 'Error frame'], node: '.......'},
{name: 'Retransmitt counter', wave: '=...=......=......=...', data: ['0', '1', '2', '0'], node: '.......'},
{name: 'Retransmitt limit', wave: '=.....................', data: ['2'], node: '.......'},
{name: 'Transmission type', wave: 'x=....x.=....x.=....x.', data: ['Initial transmission', 'First re-transmission', 'Second re-transmission'], node: '.......'},
{name: 'Operational state', wave: '=5....=.5....=.5....=.', data: ['Idle', 'Transmitter', 'Idle', 'Transmitter', 'Idle', 'Transmitter', 'Idle'], node: '.......'},
{name: 'TXT Buffer state', wave: '=4..=...4..=...4..=...', data: ['Ready', 'TX in Progress', 'Ready', 'TX in Progress', 'Ready', 'TX in Progress','TX Error'], node: '.......'},
],
//edge:['a<->b', 'c<->d', 'e~>f Destuff', 'f~>g Process', 'g~>i Stuff'],
}
{signal: [
{name: 'CAN Bus', wave: '13..4.1.3...4.1.3..4.1.', data: ['CAN frame', 'Error frame', 'CAN frame', 'Error frame', 'CAN frame', 'Error frame'], node: '.......'},
{name: 'Retransmitt counter', wave: '=...=......=.......=...', data: ['0', '1', '2', '0'], node: '.......'},
{name: 'Retransmitt limit', wave: '=......................', data: ['2'], node: '.......'},
{name: 'Arbitration lost', wave: '0..........10..........', data: ['2'], node: '.......'},
{name: 'Transmission type', wave: 'x=....x.=.....x.=....x.', data: ['Initial transmission', 'First re-transmission', 'Second re-transmission'], node: '.......'},
{name: 'Operational state', wave: '=5....=.5..3..=.5....=.', data: ['Idle', 'Transmitter', 'Idle', 'Transmitter', 'Receiver', 'Idle', 'Transmitter', 'Idle'], node: '.......'},
{name: 'TXT Buffer state', wave: '=4..=...4..=....4..=...', data: ['Ready', 'TX in Progress', 'Ready', 'TX in Progress', 'Ready', 'TX in Progress','TX Error'], node: '.......'},
],
//edge:['a<->b', 'c<->d', 'e~>f Destuff', 'f~>g Process', 'g~>i Stuff'],
}
{signal: [
{name: 'CAN frame part', wave: '===.....=.3.3.3.3.4.4.=..=5..=', data: ['Idle', 'SOF', 'Arbitration', 'Control', 'Byte 1', 'Byte 2', 'Byte 3', 'Byte 4', 'Byte 5', 'Byte 6', 'CRC','','End of frame', ''],
node: '..........a.......c...e......g'},
{name: 'Store metadata', wave: '0.........pl..................', data:[''],
node: '..............................'},
{name: 'Store data', wave: '0.................pl..pl......', data:[''],
node: '..............................'},
{name: 'Reception valid', wave: '0............................p', data:[''],
node: '..........b.......d...f......h'},
],
foot: {text:
['tspan', ' Metadata + Identifier stored Yellow Data word stored Oragne Data word stored Timestamp stored'],
},
edge:['a-b','c-d', 'e-f', 'g-h'],
}
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......@@ -179,9 +179,13 @@ void ctu_can_fd_set_mode_reg(struct ctucanfd_priv *priv,
reg.s.lom = flags & CAN_CTRLMODE_LISTENONLY ?
LOM_ENABLED : LOM_DISABLED;
#ifdef CTUCANFD_TSM_AVAILABLE
if (mode->mask & CAN_CTRLMODE_3_SAMPLES)
reg.s.tsm = flags & CAN_CTRLMODE_3_SAMPLES ?
TSM_ENABLE : TSM_DISABLE;
#else
#warning TSM_ENABLE not defined
#endif
if (mode->mask & CAN_CTRLMODE_FD)
reg.s.fde = flags & CAN_CTRLMODE_FD ?
......@@ -223,7 +227,11 @@ void ctu_can_fd_abort_tx(struct ctucanfd_priv *priv)
union ctu_can_fd_command reg;
reg.u32 = 0;
#ifdef CTUCANFD_ABT_AVAILABLE
reg.s.abt = 1;
#else
#warning abt not available
#endif
priv->write_reg(priv, CTU_CAN_FD_COMMAND, reg.u32);
}
......@@ -286,7 +294,7 @@ const struct can_bittiming_const ctu_can_fd_bit_timing_max = {
.tseg2_max = 63,
.sjw_max = 31,
.brp_min = 1,
.brp_max = 255,
.brp_max = 8,
.brp_inc = 1,
};
......@@ -298,7 +306,7 @@ const struct can_bittiming_const ctu_can_fd_bit_timing_data_max = {
.tseg2_max = 31,
.sjw_max = 31,
.brp_min = 1,
.brp_max = 255,
.brp_max = 2,
.brp_inc = 1,
};
......
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......@@ -144,11 +144,11 @@ int main(int argc, char *argv[])
apb_read(CTU_CAN_FD_DEVICE_ID);
CHECK(0x0201CAFD, "CAN ID reg mismatch (just after HW reset)");
CHECK(0x0202CAFD, "CAN ID reg mismatch (just after HW reset)");
apb_write(CTU_CAN_FD_BTR, 0xFFFFFFFF, 0b1111);
apb_read(CTU_CAN_FD_DEVICE_ID);
CHECK(0x0201CAFD, "CAN ID reg mismatch");
CHECK(0x0202CAFD, "CAN ID reg mismatch");
apb_read(CTU_CAN_FD_BTR);
CHECK(0xFFFFFFFF, "readback mismatch");
......
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********************************************************************************
** Generating Lyx docs for VHDL entity interfaces!
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Python version is: python3.6
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Processing prescaler entity
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../doc/template.lyx
Subproject commit 4e78535d62f76ae5a0b91819ab6cbb914cba4662
Subproject commit 0d50624a518f7b6eac84fc297664c4d0c3458910
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