Commit 394cdcbb authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added optional transmission at given time

as pre-synthesis generic
parent 3eac7540
......@@ -1376,7 +1376,7 @@ status open
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="4">
<lyxtabular version="3" rows="10" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
......@@ -1723,6 +1723,44 @@ true
Core should support Range Identifier Filter
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tx_time_sup
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
boolean
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
true
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Core should supprt frame transmisison at exact time
\end_layout
\end_inset
</cell>
</row>
......@@ -19615,7 +19653,28 @@ TX Arbitrator circuit covers the functionality of frame selection between
than value in TX_DATA_2 and TX_DATA_3 words of the buffer.
Thus the Frame is only selected at the moment when external timestamp has
elapsed the reuqired transmission time.
The circuit combinationally propagates the metadata about the frame (Frame
Support of this behaviour is configurable via
\begin_inset Quotes eld
\end_inset
tx_time_sup
\begin_inset Quotes erd
\end_inset
generic.
If set to
\begin_inset Quotes eld
\end_inset
false
\begin_inset Quotes erd
\end_inset
frame is transmitted as soon as inserted to the TXT Buffer.
\end_layout
\begin_layout Plain Layout
The circuit combinationally propagates the metadata about the frame (Frame
format, DLC, Frame type, Identifier) on the output.
The frame is selected combinationally and once the CAN Core acknowledges
that metadata were stored in TranBuffer, it waits until the frame transmission
......@@ -37888,12 +37947,30 @@ BRS Bit-rate shift.
\end_layout
\begin_layout Description
TS_VAL An External timestamp value when controller should attempt to start
frame transmission.
TS_VAL These word have meaning only if
\begin_inset Quotes eld
\end_inset
tx_time_sup=true
\begin_inset Quotes erd
\end_inset
.
An External timestamp value when controller should attempt to start frame
transmission.
If bus is Idle then transmission will start within next bit time.
Otherwise, it will start as soon as bus is idle.
If the frame should be transmitted immediately all zeroes must be written
into these two registers.
If
\begin_inset Quotes eld
\end_inset
tx_time_sup=false
\begin_inset Quotes erd
\end_inset
then frame is transmitted as soon as bus is idle.
\end_layout
\begin_layout Description
......@@ -1376,7 +1376,7 @@ status open
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="4">
<lyxtabular version="3" rows="10" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
......@@ -1723,6 +1723,44 @@ true
Core should support Range Identifier Filter
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tx_time_sup
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
boolean
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
true
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Core should supprt frame transmisison at exact time
\end_layout
\end_inset
</cell>
</row>
......@@ -19615,7 +19653,28 @@ TX Arbitrator circuit covers the functionality of frame selection between
than value in TX_DATA_2 and TX_DATA_3 words of the buffer.
Thus the Frame is only selected at the moment when external timestamp has
elapsed the reuqired transmission time.
The circuit combinationally propagates the metadata about the frame (Frame
Support of this behaviour is configurable via
\begin_inset Quotes eld
\end_inset
tx_time_sup
\begin_inset Quotes erd
\end_inset
generic.
If set to
\begin_inset Quotes eld
\end_inset
false
\begin_inset Quotes erd
\end_inset
frame is transmitted as soon as inserted to the TXT Buffer.
\end_layout
\begin_layout Plain Layout
The circuit combinationally propagates the metadata about the frame (Frame
format, DLC, Frame type, Identifier) on the output.
The frame is selected combinationally and once the CAN Core acknowledges
that metadata were stored in TranBuffer, it waits until the frame transmission
......@@ -37888,8 +37947,17 @@ BRS Bit-rate shift.
\end_layout
\begin_layout Description
TS_VAL An External timestamp value when controller should attempt to start
frame transmission.
TS_VAL These word have meaning only if
\begin_inset Quotes eld
\end_inset
tx_time_sup=true
\begin_inset Quotes erd
\end_inset
.
An External timestamp value when controller should attempt to start frame
transmission.
If bus is Idle then transmission will start within next bit time.
Otherwise, it will start as soon as bus is idle.
If the frame should be transmitted immediately all zeroes must be written
......@@ -44994,6 +45062,8 @@ TX_Arbitrator
\end_layout
\begin_layout Standard
\color red
TX_Arbitrator testbench independently generates inputs to the TX Arbitrator
in input_gen process.
Since the whole circuit is only combinational it provides immediate (in
......@@ -45026,6 +45096,8 @@ TX_Buffer
\end_layout
\begin_layout Standard
\color red
TXT buffer unit test instantiates two DUTs with IDs 1 and 2 as in CAN FD
IP.
The difference is that one TXT buffer is set to support FD frames, the
......@@ -59,7 +59,10 @@ use work.ID_transfer.all;
-- equal and then message with lower identifier is selected!
--------------------------------------------------------------------------------
entity txArbitrator is
entity txArbitrator is
generic(
tx_time_sup : boolean := true
);
port(
------------------------
-- Clock and reset
......@@ -228,9 +231,17 @@ begin
ident2 <= txt2buf_info_in(TXT_IDW_HIGH-3 downto TXT_IDW_LOW);
--Comparator methods for 64 bit vectors
mt1_lt_mt2 <= less_than(mess_time1,mess_time2);
mt1_lt_ts <= less_than(mess_time1,timestamp);
mt2_lt_ts <= less_than(mess_time2,timestamp);
tx_gen_true:if (tx_time_sup=true) generate
mt1_lt_mt2 <= less_than(mess_time1,mess_time2);
mt1_lt_ts <= less_than(mess_time1,timestamp);
mt2_lt_ts <= less_than(mess_time2,timestamp);
end generate;
tx_gen_false:if (tx_time_sup=false) generate
mt1_lt_mt2 <= true;
mt1_lt_ts <= true;
mt2_lt_ts <= true;
end generate;
------------------------------------------------------------------------------
--Message can be transmitted when transmitt timestamp is lower than the actual
......
......@@ -81,6 +81,7 @@ entity CAN_top_level is
constant sup_filtB : boolean := true;
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant tx_time_sup : boolean := true;
constant logger_size : natural range 0 to 512 := 8
);
port(
......@@ -575,6 +576,9 @@ begin
);
tx_arb_comp : txArbitrator
generic map(
tx_time_sup => tx_time_sup
)
port map(
clk_sys => clk_sys,
res_n => res_n,
......
......@@ -61,6 +61,7 @@ package CANcomponents is
constant sup_filtB : boolean := true;
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant tx_time_sup : boolean := true;
constant logger_size : natural --range 0 to 512:=8
);
port(
......@@ -227,6 +228,9 @@ package CANcomponents is
-- TXT Arbitrator module
------------------------------------------------------------------------------
component txArbitrator is
generic(
tx_time_sup : boolean := true
);
port(
signal clk_sys : in std_logic;
signal res_n : in std_logic;
......
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