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Commit 38980abf authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Reoranized license headers to be compatible with license 

updater script
parent ea6e6018
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Showing with 378 additions and 377 deletions
src/Buffers_Message_Handling/messageFilter.vhd
View file @ 38980abf
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.ID_transfer.all;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -33,17 +26,8 @@ use work.ID_transfer.all;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- Revision History:
--
-- July 2015 Created file
-- 17.1.2016 Added ID change from register value to decimal value for range
-- filter comparison
-- 1.6.2016 Fixed wrong enable decoding from driving bus signals! Filters
-- were disabled but
-- frame was anyway propagated to the output!
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Message filter for recieved data. Combinational circuit with valid data re-
......@@ -56,6 +40,21 @@ use work.ID_transfer.all;
-- it is considered as valid. Frame type (CAN Basic, CAN Extended, CAN FD Basic)
-- are also selectable for filtering.
--------------------------------------------------------------------------------
-- Revision History:
-- July 2015 Created file
-- 17.1.2016 Added ID change from register value to decimal value for range
-- filter comparison
-- 1.6.2016 Fixed wrong enable decoding from driving bus signals! Filters
-- were disabled but
-- frame was anyway propagated to the output!
--------------------------------------------------------------------------------
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.ID_transfer.all;
entity messageFilter is
generic
......
src/Buffers_Message_Handling/rxBuffer.vhd
View file @ 38980abf
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use ieee.std_logic_unsigned.All;
use work.CANconstants.all;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -32,8 +26,23 @@ use work.CANconstants.all;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- Revision History:
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Recieve buffer for messages. RAM memory type of N*32 bit words. Reading of
-- data from registers done word by word. In registers reading implemented in
-- the way that one read moves to the next word. Storing the message into the
-- buffer is sequential operation started with valid rec_message_valid for one
-- clock cycle. In following up to 20 clock cycles recieved data has to be va-
-- lid to be fully stored
--
-- Note:This is guaranteed from CAN Core. rec_message_valid is active in the
-- end of EOF field. Intermission field follows with 11 bit times (minimum 55
-- clock cycles) where recieved data are not changed, only overload condition
-- may be signallised!
--------------------------------------------------------------------------------
-- Revision History:
-- July 2015 Created file
-- 18.12.2015 RX Buffer inference from Flip-flops changed to native SRAM me-
-- mory on FPGA. Dual port memory used for this purpose (sync
......@@ -79,20 +88,11 @@ use work.CANconstants.all;
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Recieve buffer for messages. RAM memory type of N*32 bit words. Reading of
-- data from registers done word by word. In registers reading implemented in
-- the way that one read moves to the next word. Storing the message into the
-- buffer is sequential operation started with valid rec_message_valid for one
-- clock cycle. In following up to 20 clock cycles recieved data has to be va-
-- lid to be fully stored
--
-- Note:This is guaranteed from CAN Core. rec_message_valid is active in the
-- end of EOF field. Intermission field follows with 11 bit times (minimum 55
-- clock cycles) where recieved data are not changed, only overload condition
-- may be signallised!
--------------------------------------------------------------------------------
Library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;
use ieee.std_logic_unsigned.All;
use work.CANconstants.all;
entity rxBuffer is
GENERIC(
......
src/Buffers_Message_Handling/txArbitrator.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.ID_transfer.all;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -33,8 +26,18 @@ use work.ID_transfer.all;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Circuit for selecting the valid message for CAN Core from two TXT buffer in-
-- puts. Circuit compares the timestamp of the message with input timestamp
-- (actual time) and allows the message to be propagated to the CAN Core when
-- the time Stamp of message is higher than actual timestamp! This realises the
-- functionality of sending the message in exact time! When both timeStamp are
-- equal and then message with lower identifier is selected!
--------------------------------------------------------------------------------
-- Revision History:
--
-- July 2015 Created file
-- 17.1.2016 Added ID change from register value to decimal value for case
-- when identifier needs to decide about priority message (Time
......@@ -56,15 +59,12 @@ use work.ID_transfer.all;
-- time and save some LUTs.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Circuit for selecting the valid message for CAN Core from two TXT buffer in-
-- puts. Circuit compares the timestamp of the message with input timestamp
-- (actual time) and allows the message to be propagated to the CAN Core when
-- the time Stamp of message is higher than actual timestamp! This realises the
-- functionality of sending the message in exact time! When both timeStamp are
-- equal and then message with lower identifier is selected!
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.ID_transfer.all;
entity txArbitrator is
generic(
......
src/Buffers_Message_Handling/txtBuffer.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -32,6 +26,15 @@ use work.CANconstants.all;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Transmit message buffer. Access to TX_DATA_REG of user registers is combi-
-- nationally mapped to the TXT Buffers. User is storing the data directly into
-- the TX buffer. Once the user allows to transmitt from the buffer, content of
-- the buffer is validated and "empty" is cleared.
--------------------------------------------------------------------------------
-- Revision History:
--
-- July 2015 Created file
......@@ -47,13 +50,11 @@ use work.CANconstants.all;
-- reource reduction was achieved.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Transmit message buffer. Access to TX_DATA_REG of user registers is combi-
-- nationally mapped to the TXT Buffers. User is storing the data directly into
-- the TX buffer. Once the user allows to transmitt from the buffer, content of
-- the buffer is validated and "empty" is cleared.
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
entity txtBuffer is
generic(
......
src/Bus_Timing_Synchronisation/brs_comp.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -33,10 +26,6 @@ USE WORK.CANconstants.ALL;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- Revision History:
--
-- July 2015 Created file
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
......@@ -64,6 +53,10 @@ USE WORK.CANconstants.ALL;
-- would be set at the beginning of the "switching bit" and prescaler would
-- use hard-coded value of time quanta during ph1 and ph2 bit times.
--------------------------------------------------------------------------------
-- Revision History:
-- July 2015 Created file
--
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
......
src/Bus_Timing_Synchronisation/busSync.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -33,8 +26,22 @@ USE WORK.CANconstants.ALL;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- Revision History:
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- 1. Implements Generic Synchronisation chain for incoming data
-- 2. Detects appropriate edge for synchronisation!!
-- 3. Measure Transciever delay compensation on command
-- 4. Sample bus values in sample point of Bit time:
-- a) By normal sampling, at position of sample point (Transciever,reciever)
-- b) In secondary sample point for Transciever of CAN FD Data Phase
-- 5. Detect bit Error by comparing transmitted values and Sampled values!
--
--Note: this bit error detection used in the end only for data phase transciever
-- of CAN FD Phase! In other cases bit error is detected inside CAN-Core by
-- comparing transmitted and recieved bit.
--------------------------------------------------------------------------------
-- July 2015 Created file
-- 19.12.2015 Added tripple sampling mode. Furthermore sampling is disabled
-- when whole controller is disabled
......@@ -64,20 +71,11 @@ USE WORK.CANconstants.ALL;
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- 1. Implements Generic Synchronisation chain for incoming data
-- 2. Detects appropriate edge for synchronisation!!
-- 3. Measure Transciever delay compensation on command
-- 4. Sample bus values in sample point of Bit time:
-- a) By normal sampling, at position of sample point (Transciever,reciever)
-- b) In secondary sample point for Transciever of CAN FD Data Phase
-- 5. Detect bit Error by comparing transmitted values and Sampled values!
--
--Note: this bit error detection used in the end only for data phase transciever
-- of CAN FD Phase! In other cases bit error is detected inside CAN-Core by
-- comparing transmitted and recieved bit.
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
entity busSync is
GENERIC (
......
src/Bus_Timing_Synchronisation/prescaler_v3.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
use work.brs_comp_package.all;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -33,6 +26,21 @@ use work.brs_comp_package.all;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- v.3 of Prescaler circuit. Due to synchronisation issues with two bit rate
-- counters during switching bit Rates only one counter used. Due to this im-
-- plementation *_nbt, *_dbt signals availiable only when sp_control indicates
-- this bit rate is actual transmit/recieve bit rate! Bit timing is set from
-- driving bus. Contol of generated bit time is made via sp_control signal.
-- Synchronisation is enabled and control via sync_control input. The edge used
-- for synchronisation is signalised by active signal sync_edge. Synchronisation
-- type has to be valid on sync_control. When hard synchronisation appears then
-- separate state is entered which handles correct sample and sync signals ge-
-- neration so that no error appears during hard synchronisation!
--------------------------------------------------------------------------------
-- Revision History:
--
-- June 2015 Version 1 of circuit
......@@ -90,19 +98,12 @@ use work.brs_comp_package.all;
-- During the bit where bit rate switch occured.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- v.3 of Prescaler circuit. Due to synchronisation issues with two bit rate
-- counters during switching bit Rates only one counter used. Due to this im-
-- plementation *_nbt, *_dbt signals availiable only when sp_control indicates
-- this bit rate is actual transmit/recieve bit rate! Bit timing is set from
-- driving bus. Contol of generated bit time is made via sp_control signal.
-- Synchronisation is enabled and control via sync_control input. The edge used
-- for synchronisation is signalised by active signal sync_edge. Synchronisation
-- type has to be valid on sync_control. When hard synchronisation appears then
-- separate state is entered which handles correct sample and sync signals ge-
-- neration so that no error appears during hard synchronisation!
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
use work.brs_comp_package.all;
entity prescaler_v3 is
PORT(
......
src/CAN_Core/CRC.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -32,15 +26,6 @@ use work.CANconstants.all;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- Revision History:
--
-- June 2015 Created file
-- 28.5.2016 Starting polynomial changed for crc 17 and crc 21. Highest bit
-- is now fixed in logic one to be compliant with CAN ISO FD. It
-- will be needed to implement both ways still since ISO and
-- non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17
-- and crc21 polynomial
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
......@@ -54,6 +39,22 @@ use work.CANconstants.all;
--
-- Refer to CAN 2.0 or CAN FD Specification for CRC calculation algorythm --
--------------------------------------------------------------------------------
-- Revision History:
-- June 2015 Created file
-- 28.5.2016 Starting polynomial changed for crc 17 and crc 21. Highest bit
-- is now fixed in logic one to be compliant with CAN ISO FD. It
-- will be needed to implement both ways still since ISO and
-- non-ISO FD will be changable via configuration bit!
-- 4.6.2016 Added drv_is_fd to cover differencce in highest bit of crc17
-- and crc21 polynomial
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
entity canCRC is
generic(
......
src/CAN_Core/bitDeStuffing.vhd
View file @ 38980abf
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use WORK.CANconstants.all;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -32,8 +26,18 @@ use WORK.CANconstants.all;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--Purpose:
-- Bit destuffing circuit. Data sampled always with valid trig_spl_1 signal.
-- Length of bitStuffing controlled via stuff_length input. Stuff error signa-
-- lises Error when the stuff rule is not valid (stuff_lenght+1) consecutive
-- bits of the same polarity. Signal destuffed indicates that current output
-- bit is not valid data bit, but is destuffed bit taken out from input data
-- stream!
--------------------------------------------------------------------------------
-- Revision History:
--
-- July 2015 Created file
-- 19.5.2016 1. Added Stuff bit counter to cover ISO FD extra field!
-- 2. Edge detection 0->1 added at fixed_stuff input. Once edge
......@@ -62,16 +66,11 @@ use WORK.CANconstants.all;
-- ffing in the start of FD CRC. Fixed bit-destuff should win!
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--Purpose:
-- Bit destuffing circuit. Data sampled always with valid trig_spl_1 signal.
-- Length of bitStuffing controlled via stuff_length input. Stuff error signa-
-- lises Error when the stuff rule is not valid (stuff_lenght+1) consecutive
-- bits of the same polarity. Signal destuffed indicates that current output
-- bit is not valid data bit, but is destuffed bit taken out from input data
-- stream!
--------------------------------------------------------------------------------
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use WORK.CANconstants.all;
entity bitDestuffing is
port(
......
src/CAN_Core/bitStuffing_v2.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -32,6 +26,22 @@ USE WORK.CANconstants.ALL;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Simple bit stuffing circuit with HandShake protocol. When bit is stuffed
-- transciever (CAN Core) has to stop transcieving for one bit time. data_halt
-- output is set to logic 1 when bit is stuffed.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Second version of bit Stuffing circuit. Enables configurable stuff length.
-- Operation starts when enable='1'. Valid data already has to be on data_in
-- then. Operates with triggering signal tran_trig_1 Fixed Stuffing method can
-- be used by setting logic on fixed_stuff input. In fixed stuff inverse bit is
-- inserted after every stuff_length bits, even if their polarity is not equal!
--------------------------------------------------------------------------------
-- Revision History:
--
-- June 2015 Created file
......@@ -51,20 +61,11 @@ USE WORK.CANconstants.ALL;
-- in the start of FD CRC. Fixed bit-stuff should win!
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Simple bit stuffing circuit with HandShake protocol. When bit is stuffed
-- transciever (CAN Core) has to stop transcieving for one bit time. data_halt
-- output is set to logic 1 when bit is stuffed.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Second version of bit Stuffing circuit. Enables configurable stuff length.
-- Operation starts when enable='1'. Valid data already has to be on data_in
-- then. Operates with triggering signal tran_trig_1 Fixed Stuffing method can
-- be used by setting logic on fixed_stuff input. In fixed stuff inverse bit is
-- inserted after every stuff_length bits, even if their polarity is not equal!
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
entity bitStuffing_v2 is
port(
......
src/CAN_Core/core_top.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.CANcomponents.ALL;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -33,8 +26,17 @@ use work.CANcomponents.ALL;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Top level entity of CAN Core covering whole functionality of CAN FD Protocol
-- Instantiates: 1*protocol_control, 1*operation_control, 1*bitStuffing_v2,
-- 1*bitDestuffing, 2*CRC, 1* tranBuffer
-- Logic for switching sampling and synchronisation signals implemented here
-- stat_bus assignment implemented here!
--------------------------------------------------------------------------------
-- Revision History:
--
-- July 2015 Created file
-- 4.6.2016 Added drv_bus connection to the crc circuit to cover the diffe-
-- rence between ISO FD and NON ISO FD. CRC polynomial changed to
......@@ -63,14 +65,12 @@ use work.CANcomponents.ALL;
-- being used!
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Top level entity of CAN Core covering whole functionality of CAN FD Protocol
-- Instantiates: 1*protocol_control, 1*operation_control, 1*bitStuffing_v2,
-- 1*bitDestuffing, 2*CRC, 1* tranBuffer
-- Logic for switching sampling and synchronisation signals implemented here
-- stat_bus assignment implemented here!
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
use work.CANconstants.all;
use work.CANcomponents.ALL;
entity core_top is
PORT(
......
src/CAN_Core/faultConf.vhd
View file @ 38980abf
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
--------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
......@@ -32,18 +26,6 @@ USE WORK.CANconstants.ALL;
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- Revision History:
--
-- June 2015 Created file
-- 19.6.2016 Modified counters for error couting in both FD and NORMAL mode.
-- Counters extended to 16 bits wide, to match the format in the
-- registers!
-- 27.6.2016 Bug fix. Changed error warning limit reached detection to greater
-- than and equal instead of only equal.
-- 30.6.2016 Bug fix. Added equal or greater to fault confinement error
-- passive state. According to CAN spec. error counter value equal
-- or greater than 128 is error passive, not only greater than!
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
......@@ -57,6 +39,24 @@ USE WORK.CANconstants.ALL;
-- ning limit and transition to error_pssive are also parameters given by dri-
-- ving bus. Default values are compliant with CAN FD standard.
--------------------------------------------------------------------------------
-- Revision History:
-- June 2015 Created file
-- 19.6.2016 Modified counters for error couting in both FD and NORMAL mode.
-- Counters extended to 16 bits wide, to match the format in the
-- registers!
-- 27.6.2016 Bug fix. Changed error warning limit reached detection to greater
-- than and equal instead of only equal.
-- 30.6.2016 Bug fix. Added equal or greater to fault confinement error
-- passive state. According to CAN spec. error counter value equal
-- or greater than 128 is error passive, not only greater than!
--
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
USE ieee.std_logic_unsigned.All;
USE WORK.CANconstants.ALL;
entity faultConf is
PORT(
......