Commit 36c1e7db authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Modify reg. map and regenerate to have separate locks on BTR, BTR_FD and SSP_CFG.

parent b037651d
......@@ -4428,7 +4428,8 @@ package can_components is
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock :in std_logic;
signal lock_1 :in std_logic;
signal lock_2 :in std_logic;
signal control_registers_out :out Control_registers_out_t;
signal control_registers_in :in Control_registers_in_t
);
......
......@@ -99,7 +99,7 @@ component memory_reg is
constant reset_polarity : std_logic := '0';
constant reset_value : std_logic_vector;
constant auto_clear : std_logic_vector;
constant is_lockable : std_logic
constant is_lockable : boolean
);
port(
signal clk_sys :in std_logic;
......
......@@ -84,7 +84,12 @@ entity memory_bus_template is
signal read :in std_logic;
signal write :in std_logic;
signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
signal lock :in std_logic
------------------------------------------------------------------------
-- Lock signals
------------------------------------------------------------------------
signal lock_1 :in std_logic;
signal lock_2 :in std_logic
);
end entity memory_bus_template;
......
......@@ -61,7 +61,7 @@ entity memory_reg is
-- When set to 1, Logic 1 on 'lock' input will prevent register
-- from being written!
constant is_lockable : std_logic
constant is_lockable : boolean
);
port(
------------------------------------------------------------------------
......@@ -125,14 +125,14 @@ begin
------------------------------------------------------------------------
-- Register with write lock
------------------------------------------------------------------------
wr_sel_lock_gen : if (is_lockable = '1') generate
wr_sel_lock_gen : if (is_lockable = true) generate
wr_select(i) <= write and cs and w_be(i) and (not lock);
end generate wr_sel_lock_gen;
------------------------------------------------------------------------
-- Register without write lock
------------------------------------------------------------------------
wr_sel_no_lock_gen : if (is_lockable = '0') generate
wr_sel_no_lock_gen : if (is_lockable = false) generate
wr_select(i) <= write and cs and w_be(i);
end generate wr_sel_no_lock_gen;
......
......@@ -270,8 +270,9 @@ architecture rtl of memory_registers is
-- Internal value of output reset. This is combined res_n and MODE[RST]
signal res_out_i : std_logic;
-- Lock active (inactive only in test mode)
signal reg_lock_active : std_logic;
-- Locks active
signal reg_lock_1_active : std_logic;
signal reg_lock_2_active : std_logic;
-- Soft reset registering
signal soft_res_q : std_logic;
......@@ -406,7 +407,8 @@ begin
read => srd,
write => swr,
be => sbe,
lock => reg_lock_active,
lock_1 => reg_lock_1_active,
lock_2 => reg_lock_2_active,
control_registers_out => control_registers_out,
control_registers_in => control_registers_in
);
......@@ -414,7 +416,8 @@ begin
----------------------------------------------------------------------------
-- Several registers are locked and accessible only in Test mode!
----------------------------------------------------------------------------
reg_lock_active <= not control_registers_out.mode(TSTM_IND);
reg_lock_1_active <= not control_registers_out.mode(TSTM_IND);
reg_lock_2_active <= control_registers_out.settings(ENA_IND mod 16);
----------------------------------------------------------------------------
-- Pipeline on Soft reset register.
......
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