Commit 36917dba authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Changed buffer byte order. Lowest data byte within a word is

now on lowest address.
parent 8bc20139
......@@ -196,9 +196,11 @@
-- 6.4.2018 Added direct addressing of identifier from Protocol control.
-- In SOF TXT buffer pointer is set to identifier word and
-- Identifier is stored in the first cycle of Arbitration field.
-- 19.5.2018 Added "store_data", "store_metadata", "rec_abort" signals
-- as a storing protocol between CAN Core and RX Buffer for
-- continous storing of CAN frame during reception.
-- 19.5.2018 1. Added "store_data", "store_metadata", "rec_abort" signals
-- as a storing protocol between CAN Core and RX Buffer for
-- continous storing of CAN frame during reception.
-- 2. Added endian swap for transceived and received data to
-- have Data byte 0 at address 0.
--------------------------------------------------------------------------------
Library ieee;
......@@ -208,6 +210,8 @@ use work.CANconstants.all;
use work.CAN_FD_frame_format.all;
use work.CAN_FD_register_map.all;
use work.endian_swap.all;
entity protocolControl is
port(
-------------------
......@@ -618,6 +622,9 @@ entity protocolControl is
--Pointer directly to TXT buffer to get the data
signal txt_buf_ptr_r : natural range 0 to 19;
-- Data word to transmit after endian swapping.
signal tx_data_word : std_logic_vector(31 downto 0);
-----------------------
--CRC field registers--
......@@ -767,6 +774,9 @@ begin
txt_buf_ptr <= txt_buf_ptr_r;
sof_pulse <= sof_pulse_r;
-- TX Data word endian swap
tx_data_word <= endian_swap_32(tran_data);
-----------------------
--Auxiliarly vectors
......@@ -1795,10 +1805,9 @@ begin
if(OP_State=transciever)then
if(tran_trig='1')then
--data_tx_r <= tran_data(data_pointer);
data_tx_r <= tran_data(data_pointer mod 32);
data_tx_r <= tx_data_word(data_pointer mod 32);
--Move to the next word
-- Move to the next word
if ((data_pointer mod 32) = 0) then
if (txt_buf_ptr_r < 19) then
txt_buf_ptr_r <= txt_buf_ptr_r + 1;
......@@ -1822,22 +1831,22 @@ begin
rec_word_bind <= (rec_word_bind + 1) mod 4;
case rec_word_bind is
when 0 =>
store_data_word_r <= rec_data_sr(6 downto 0) &
data_rx &
"000000000000000000000000";
-- First byte of word, whole word is written to avoid
-- bytes from old frames!
store_data_word_r <= "000000000000000000000000" &
rec_data_sr(6 downto 0) &
data_rx;
when 1 =>
store_data_word_r(23 downto 0) <=
store_data_word_r(15 downto 8) <=
rec_data_sr(6 downto 0) &
data_rx &
"0000000000000000";
data_rx;
when 2 =>
store_data_word_r(15 downto 0) <=
store_data_word_r(23 downto 16) <=
rec_data_sr(6 downto 0) &
data_rx &
"00000000";
data_rx;
when 3 =>
store_data_word_r(7 downto 0) <=
rec_data_sr(6 downto 0)&
store_data_word_r(31 downto 24) <=
rec_data_sr(6 downto 0) &
data_rx;
when others =>
report "Unknown state" severity error;
......
......@@ -107,7 +107,8 @@ package CANconstants is
constant INC_EIGHT_CON : std_logic_vector(2 downto 0) := "010";
constant DEC_ONE_CON : std_logic_vector(2 downto 0) := "001";
constant TXT_BUFFER_COUNT : natural := 4;
-- Common definitions should not be generic at the moment
constant TXT_BUFFER_COUNT : natural := 4;
constant INT_COUNT : natural := 12;
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
--
-- Project advisors and co-authors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- Martin Jerabek <jerabma7@fel.cvut.cz>
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Package with conversion functions of byte endianess.
--------------------------------------------------------------------------------
-- Revision History:
-- 19.5.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
use work.CAN_FD_frame_format.all;
package endian_swap is
-- Register value to decimal value
function endian_swap_32(
signal input : std_logic_vector
) return std_logic_vector;
end package endian_swap;
package body endian_swap is
function endian_swap_32(
signal input : std_logic_vector
) return std_logic_vector is
begin
if (input'length /= 32) then
report "Invalid input length to endian swap" severity error;
return x"00000000";
else
return input(7 downto 0) &
input(15 downto 8) &
input(23 downto 16) &
input(31 downto 24);
end if;
end function;
end endian_swap;
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