Commit 348a10e8 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Add gating of synchronisation edge by time quanta.

This will make sure that synchronisation will not be susceptible
to glitches of less than Time quanta!
parent 0087cf26
......@@ -132,6 +132,9 @@ entity bus_sampling is
-- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic;
-- Time quanta edge
tq_edge :in std_logic;
------------------------------------------------------------------------
-- CAN Core Interface
------------------------------------------------------------------------
......@@ -456,7 +459,10 @@ begin
rx_data_wbs <= data_rx_synced;
-- As synchroniation edge, valid edge on RX Data is selected!
sync_edge <= edge_rx_valid;
-- Gated by Time Quanta edge so that edges aligned with time
-- quanta are propagated!
sync_edge <= '1' when (edge_rx_valid = '1' and tq_edge = '1') else
'0';
-- Registers to output propagation
sample_sec <= sample_sec_i;
......
......@@ -468,6 +468,9 @@ architecture rtl of can_top_level is
-- Bit time FSM state
signal bt_fsm : t_bit_time;
-- Time quanta edge
signal tq_edge : std_logic;
begin
-- <RELEASE_OFF>
......@@ -867,7 +870,8 @@ begin
tx_trigger => tx_trigger, -- OUT
-- Status outputs
bt_fsm => bt_fsm -- OUT
bt_fsm => bt_fsm, -- OUT
tq_edge => tq_edge -- OUT
);
......@@ -900,6 +904,7 @@ begin
rx_trigger => rx_triggers(1), -- IN
tx_trigger => tx_trigger, -- IN
sync_edge => sync_edge, -- OUT
tq_edge => tq_edge, -- IN
-- CAN Core Interface
tx_data_wbs => tx_data_wbs, -- IN
......
......@@ -242,6 +242,9 @@ package can_components is
-- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic;
-- Time quanta edge
tq_edge :out std_logic;
------------------------------------------------------------------------
-- CAN Core Interface
------------------------------------------------------------------------
......@@ -3461,7 +3464,10 @@ package can_components is
-----------------------------------------------------------------------
-- Bit Time FSM state
bt_fsm : out t_bit_time
bt_fsm : out t_bit_time;
-- Time quanta edge
tq_edge : out std_logic
);
end component;
......
......@@ -155,7 +155,10 @@ entity prescaler is
-- Status outputs
-----------------------------------------------------------------------
-- Bit Time FSM state
bt_fsm : out t_bit_time
bt_fsm : out t_bit_time;
-- Time quanta edge
tq_edge : out std_logic
);
end entity;
......@@ -469,6 +472,9 @@ begin
tx_trigger => tx_trigger -- OUT
);
tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else
tq_edge_dbt;
-- <RELEASE_OFF>
---------------------------------------------------------------------------
---------------------------------------------------------------------------
......
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