Commit 348a10e8 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Add gating of synchronisation edge by time quanta.

This will make sure that synchronisation will not be susceptible
to glitches of less than Time quanta!
parent 0087cf26
...@@ -131,6 +131,9 @@ entity bus_sampling is ...@@ -131,6 +131,9 @@ entity bus_sampling is
-- Valid synchronisation edge appeared (Recessive to Dominant) -- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic; sync_edge :out std_logic;
-- Time quanta edge
tq_edge :in std_logic;
------------------------------------------------------------------------ ------------------------------------------------------------------------
-- CAN Core Interface -- CAN Core Interface
...@@ -450,15 +453,18 @@ begin ...@@ -450,15 +453,18 @@ begin
); );
-- Output data propagation - Pipe directly - no delay -- Output data propagation - Pipe directly - no delay
can_tx <= tx_data_wbs; can_tx <= tx_data_wbs;
-- RX Data for bit destuffing - Output of re-synchroniser. -- RX Data for bit destuffing - Output of re-synchroniser.
rx_data_wbs <= data_rx_synced; rx_data_wbs <= data_rx_synced;
-- As synchroniation edge, valid edge on RX Data is selected! -- As synchroniation edge, valid edge on RX Data is selected!
sync_edge <= edge_rx_valid; -- Gated by Time Quanta edge so that edges aligned with time
-- quanta are propagated!
sync_edge <= '1' when (edge_rx_valid = '1' and tq_edge = '1') else
'0';
-- Registers to output propagation -- Registers to output propagation
sample_sec <= sample_sec_i; sample_sec <= sample_sec_i;
end architecture; end architecture;
\ No newline at end of file
...@@ -467,6 +467,9 @@ architecture rtl of can_top_level is ...@@ -467,6 +467,9 @@ architecture rtl of can_top_level is
------------------------------------------------------------------------ ------------------------------------------------------------------------
-- Bit time FSM state -- Bit time FSM state
signal bt_fsm : t_bit_time; signal bt_fsm : t_bit_time;
-- Time quanta edge
signal tq_edge : std_logic;
begin begin
...@@ -867,7 +870,8 @@ begin ...@@ -867,7 +870,8 @@ begin
tx_trigger => tx_trigger, -- OUT tx_trigger => tx_trigger, -- OUT
-- Status outputs -- Status outputs
bt_fsm => bt_fsm -- OUT bt_fsm => bt_fsm, -- OUT
tq_edge => tq_edge -- OUT
); );
...@@ -900,6 +904,7 @@ begin ...@@ -900,6 +904,7 @@ begin
rx_trigger => rx_triggers(1), -- IN rx_trigger => rx_triggers(1), -- IN
tx_trigger => tx_trigger, -- IN tx_trigger => tx_trigger, -- IN
sync_edge => sync_edge, -- OUT sync_edge => sync_edge, -- OUT
tq_edge => tq_edge, -- IN
-- CAN Core Interface -- CAN Core Interface
tx_data_wbs => tx_data_wbs, -- IN tx_data_wbs => tx_data_wbs, -- IN
......
...@@ -241,6 +241,9 @@ package can_components is ...@@ -241,6 +241,9 @@ package can_components is
-- Valid synchronisation edge appeared (Recessive to Dominant) -- Valid synchronisation edge appeared (Recessive to Dominant)
sync_edge :out std_logic; sync_edge :out std_logic;
-- Time quanta edge
tq_edge :out std_logic;
------------------------------------------------------------------------ ------------------------------------------------------------------------
-- CAN Core Interface -- CAN Core Interface
...@@ -3461,7 +3464,10 @@ package can_components is ...@@ -3461,7 +3464,10 @@ package can_components is
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- Bit Time FSM state -- Bit Time FSM state
bt_fsm : out t_bit_time bt_fsm : out t_bit_time;
-- Time quanta edge
tq_edge : out std_logic
); );
end component; end component;
......
...@@ -155,7 +155,10 @@ entity prescaler is ...@@ -155,7 +155,10 @@ entity prescaler is
-- Status outputs -- Status outputs
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- Bit Time FSM state -- Bit Time FSM state
bt_fsm : out t_bit_time bt_fsm : out t_bit_time;
-- Time quanta edge
tq_edge : out std_logic
); );
end entity; end entity;
...@@ -226,7 +229,7 @@ architecture rtl of prescaler is ...@@ -226,7 +229,7 @@ architecture rtl of prescaler is
-- Time quanta edges -- Time quanta edges
signal tq_edge_nbt : std_logic; signal tq_edge_nbt : std_logic;
signal tq_edge_dbt : std_logic; signal tq_edge_dbt : std_logic;
-- Sample trigger request (in sample point) -- Sample trigger request (in sample point)
signal rx_trig_req : std_logic; signal rx_trig_req : std_logic;
...@@ -468,6 +471,9 @@ begin ...@@ -468,6 +471,9 @@ begin
rx_triggers => rx_triggers, -- OUT rx_triggers => rx_triggers, -- OUT
tx_trigger => tx_trigger -- OUT tx_trigger => tx_trigger -- OUT
); );
tq_edge <= tq_edge_nbt when (sp_control = NOMINAL_SAMPLE) else
tq_edge_dbt;
-- <RELEASE_OFF> -- <RELEASE_OFF>
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
......
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