Commit 2e689716 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Removed pyXact generator files.

parent 60c1376a
...@@ -33,11 +33,11 @@ ...@@ -33,11 +33,11 @@
/* This file is autogenerated, DO NOT EDIT! */ /* This file is autogenerated, DO NOT EDIT! */
#ifndef __CTU_CAN_FD_REGS__ #ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
#define __CTU_CAN_FD_REGS__ #define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
/* Regs memory map */ /* CAN_Registers memory map */
enum ctu_can_fd_regs { enum ctu_can_fd_can_registers {
CTU_CAN_FD_DEVICE_ID = 0x0, CTU_CAN_FD_DEVICE_ID = 0x0,
CTU_CAN_FD_VERSION = 0x2, CTU_CAN_FD_VERSION = 0x2,
CTU_CAN_FD_MODE = 0x4, CTU_CAN_FD_MODE = 0x4,
...@@ -147,7 +147,9 @@ union ctu_can_fd_mode_command_status_settings { ...@@ -147,7 +147,9 @@ union ctu_can_fd_mode_command_status_settings {
uint32_t rrb : 1; uint32_t rrb : 1;
uint32_t cdo : 1; uint32_t cdo : 1;
uint32_t ercrst : 1; uint32_t ercrst : 1;
uint32_t reserved_15_13 : 3; uint32_t rxfcrst : 1;
uint32_t txfcrst : 1;
uint32_t reserved_15 : 1;
/* STATUS */ /* STATUS */
uint32_t rxne : 1; uint32_t rxne : 1;
uint32_t dor : 1; uint32_t dor : 1;
...@@ -177,7 +179,9 @@ union ctu_can_fd_mode_command_status_settings { ...@@ -177,7 +179,9 @@ union ctu_can_fd_mode_command_status_settings {
uint32_t txnf : 1; uint32_t txnf : 1;
uint32_t dor : 1; uint32_t dor : 1;
uint32_t rxne : 1; uint32_t rxne : 1;
uint32_t reserved_15_13 : 3; uint32_t reserved_15 : 1;
uint32_t txfcrst : 1;
uint32_t rxfcrst : 1;
uint32_t ercrst : 1; uint32_t ercrst : 1;
uint32_t cdo : 1; uint32_t cdo : 1;
uint32_t rrb : 1; uint32_t rrb : 1;
......
# To generate register map package with register addresses and bit offset:
python3.6 gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_Registers --wordWidth 32 --outFile ../src/Libraries/CAN_FD_register_map.vhd --packName CAN_FD_register_map
# To generate frame format related constants
python3.6 gen_vhdl_package.py --licPath ../LICENSE --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_Frame_format --wordWidth 32 --outFile ../src/Libraries/CAN_FD_frame_format.vhd --packName CAN_FD_frame_format
# To generate C header files (register map and frame format)
python3.6 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_Registers --wordWidth 32 --outFile ../driver/ctu_can_fd_regs.h --headName regs
python3.6 gen_c_header.py --licPath ../lic/gpl_v2.txt --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_Frame_format --wordWidth 32 --outFile ../driver/ctu_can_fd_frame.h --headName frame
# To generate Lyx docu for register map
python3.6 gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_Registers --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/registerMap.lyx --chaptName "Register map" --genRegions True --genFiDesc True
# To generate Lyx docu for CAN frame
python3.6 gen_lyx_docu.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --memMap CAN_Frame_format --wordWidth 32 --lyxTemplate ../doc/core/template.lyx --outFile ../doc/core/CANFrameFormat.lyx --chaptName "CAN Frame format" --genRegions False --genFiDesc True
#########################################
## To perform complete update
#########################################
python3.5 update_reg_map.py --xactSpec ../spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml --updVHDL True --updHeader True --updDocs True
# Ignore Python generated classes
__pycache__*
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2018 Ondrej Ille <ondrej.ille@gmail.com>
##
## Class for generation of C header from IP-XACT specification. Register
## map addresses, bit field offsets and enums are generated. Two separate
## register maps can be specified: one for bit fields, one for addresses.
##
## In case of CAN FD Core the register map is specified with two register
## maps. 8-bit map with register fields described. 32 bit register maps with
## name aliases used on 32 bit Avalon and AXI.
##
## Revision history:
## 24.01.2018 Implemented the script
## 27.11.2018 Changed script to be a class
##
################################################################################
import argparse
import sys
import time
import importlib.util
import os
import inspect
import math
from .gen_lib import *
from .ip_xact.h_addr_generator import HeaderAddrGenerator
class HeaderAddrGeneratorWrapper():
# File with license which should be placed to header of the all source code files
licPath = ""
# Path to a IP-XACT specification file with register maps
xactSpec = ""
# Name of the IP-XACT Memory map which should be used for VHDL package generatio.
memMap = None
# Size of the access bus word. Register bit field offsets are concatenated into
# word width size instead of simple offset from beginning of register. (E.g. 32 bit ->
# bitfields from first four 8-bit register are concatenated into 32 bit values)
wordWidth = 32
# Name of the VHDL package to create
headName = ""
# Output where to write the VHDL package.
outFile = ""
def do_update(self):
with open(self.xactSpec) as f:
name = None
offset = 0
addrMap = None
fieldMap = None
component = Component()
component.load(f)
with open_output(self.outFile) as of:
headerGen = HeaderAddrGenerator(component, self.memMap, self.wordWidth)
headerGen.set_of(of)
if (self.licPath != ""):
lic_text = load_license(self.licPath)
write_license(lic_text, '*', of)
headerGen.prefix = "ctu_can_fd"
headerGen.create_addrMap_package(self.headName)
headerGen.commit_to_file()
if __name__ == '__main__':
self.do_update()
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2018 Ondrej Ille <ondrej.ille@gmail.com>
##
## Class for generation of Lyx document from IP-XACT specification.
##
## In case of CAN FD Core the register map is specified with two register
## maps. 8-bit map with register fields described. 32 bit register maps with
## name aliases used on 32 bit Avalon and AXI.
##
## Revision history:
## 31.01.2018 Implemented the script
## 27.11.2018 Changed script to be a class
##
################################################################################
import argparse
import sys
import time
import importlib.util
import os
import inspect
import math
from .gen_lib import *
from .ip_xact.lyx_addr_generator import LyxAddrGenerator
class LyxAddrGeneratorWrapper():
# Path to a IP-XACT specification file with register maps
xactSpec = ""
# Name of the IP-XACT Memory map which should be used for VHDL package generatio.
memMap = None
# Size of the access bus word. Register bit field offsets are concatenated into
# word width size instead of simple offset from beginning of register. (E.g. 32 bit ->
# bitfields from first four 8-bit register are concatenated into 32 bit values)
wordWidth = 32
# Output where to write the VHDL package.
outFile = ""
# If memory map region overview should be generated
genRegions = False
# If field descriptions should be generated
genFiDesc = False
# Lyx template path
lyxTemplate = ""
def do_update(self):
args = parse_args()
with open(self.xactSpec) as f:
name = None
offset = 0
addrMap = None
fieldMap = None
component = Component()
component.load(f)
with open_output(self.outFile) as of:
lyxGen = LyxAddrGenerator(component, self.memMap, self.wordWidth,
genRegions=self.genRegions,
genFiDesc=self.genFiDesc)
lyxGen.set_of(of)
lyxGen.load_lyx_template(self.lyxTemplate)
# Write the documentation
lyxGen.write_mem_map_both()
lyxGen.lyxGen.commit_append_lines_all()
lyxGen.commit_to_file()
if __name__ == '__main__':
self.do_update()
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
##
## Class for generation of VHDL package from IP-XACT specification. Register
## map addresses, bit field offsets and enums are generated. Two separate
## register maps can be specified: one for bit fields, one for addresses.
##
## In case of CAN FD Core the register map is specified with two register
## maps. 8-bit map with register fields described. 32 bit register maps with
## name aliases used on 32 bit Avalon and AXI.
##
## Revision history:
## 16.01.2018 Implemented the script
## 25.11.2018 Joined field and address map to a single memory map/
## Re-implemented script to be Python class
##
################################################################################
import argparse
import sys
import time
import importlib.util
import os
import inspect
import math
from .gen_lib import *
from .ip_xact.vhdl_addr_generator import VhdlAddrGenerator
class VhdlAddrGeneratorWrapper():
# File with license which should be placed to header of the all source code files
licPath = ""
# Path to a IP-XACT specification file with register maps
xactSpec = ""
# Name of the IP-XACT Memory map which should be used for VHDL package generatio.
memMap = None
# Size of the access bus word. Register bit field offsets are concatenated into
# word width size instead of simple offset from beginning of register. (E.g. 32 bit ->
# bitfields from first four 8-bit register are concatenated into 32 bit values)
wordWidth = 32
# Name of the VHDL package to create
packName = ""
# Output where to write the VHDL package.
outFile = ""
def do_update(self):
with open(self.xactSpec) as spec_file:
name = None
offset = 0
# Load IP-Xact component
component = Component()
component.load(spec_file)
with open_output(self.outFile) as of:
vhdlGen = VhdlAddrGenerator(component, self.memMap, self.wordWidth)
vhdlGen.set_of(of)
if (self.licPath != ""):
lic_text = load_license(self.licPath)
write_license(lic_text, '-', of)
vhdlGen.create_addrMap_package(self.packName)
vhdlGen.commit_to_file()
if __name__ == '__main__':
self.do_update()
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2017 Ondrej Ille <ondrej.ille@gmail.com>
##
## Class for generation of VHDL register map entity from IP-XACT
## specification.
##
## Revision history:
## 25.11.2018 Implemented the script
## 27.11.2018 Changed implementation to be a class
##
################################################################################
import argparse
import sys
import time
import importlib.util
import os
import inspect
import math
from .gen_lib import *
from .ip_xact.vhdl_reg_map_generator import VhdlRegMapGenerator
from shutil import copyfile
class VhdlRegMapGeneratorWrapper():
# File with license which should be placed to header of the all source code files
licPath = ""
# Path to a IP-XACT specification file with register maps
xactSpec = ""
# Name of the IP-XACT Memory map which should be used for VHDL package generatio.
memMap = None
# Size of the access bus word. Register bit field offsets are concatenated into
# word width size instead of simple offset from beginning of register. (E.g. 32 bit ->
# bitfields from first four 8-bit register are concatenated into 32 bit values)
wordWidth = 32
# When set to "True" read data are read with one clock cycle delay. When set to
# false read data are available within the same clock cycle
registeredRead = True
# Output directory where to write VHDL register map implementation.
outDir = ""
# Variable for loaded license Text
lic_text = ""
def write_reg_map_package(self, vhdlGen, dir_path):
"""
Create package with records for register blocks within an address block.
"""
reg_map_pkg_name = os.path.join(dir_path, vhdlGen.memMap.name.lower() + "_pkg.vhd")
of = open(reg_map_pkg_name, 'w')
vhdlGen.set_of(of)
write_license(self.lic_text, '-', of)
vhdlGen.write_reg_map_pkg()
vhdlGen.commit_to_file()
of.close()
def write_reg_map_implementation(self, vhdlGen, dir_path):
"""
Write register map implementation. Create separate entity file for
each register memory block.
"""
for block in vhdlGen.memMap.addressBlock:
print("Processing memory block: " + block.name)
if (block.usage == "register"):
file_path = os.path.join(dir_path, block.name.lower() + "_reg_map.vhd")
of = open(file_path, 'w')
vhdlGen.set_of(of)
write_license(self.lic_text, '-', of)
vhdlGen.write_reg_block(block)
vhdlGen.commit_to_file()
of.close()
else:
print("Skipping unsupported block type: " + block.usage)
print("\n")
def copy_reg_map_sources(self, vhdlGen, dir_path, destDir):
"""
Copy VHDL templates to destination directory!
"""
for templ_name, templ_path in vhdlGen.template_sources.items():
src_path = os.path.join(ROOT_PATH, templ_path)
dest_path = os.path.join(ROOT_PATH, destDir)
dest_path = os.path.join(dest_path, os.path.basename(templ_path))
copyfile(src_path, dest_path)
def do_update(self):
with open(self.xactSpec) as f:
name = None
offset = 0
# Load IP-Xact component
component = Component()
component.load(f)
# Create new VHDL register map generator
vhdlGen = VhdlRegMapGenerator(component, self.memMap, self.wordWidth)
# Load license text
self.lic_text = ""
if (self.licPath != ""):
self.lic_text = load_license(self.licPath)
# Check output directory
dir_path = os.path.join(ROOT_PATH, self.outDir)
if (not os.path.isdir(dir_path)):
print("ERROR: " + dir_path + " is not a directory")
sys.exit(1)
# Configure registered / non-registered read
if (str_arg_to_bool(self.registeredRead)):
vhdlGen.registered_read = True
else:
vhdlGen.registered_read = False
# Create common package for whole address map
self.write_reg_map_package(vhdlGen, dir_path)
# Create implementation of each register block within address map
self.write_reg_map_implementation(vhdlGen, dir_path)
# Copy source templates to destination directory
self.copy_reg_map_sources(vhdlGen, dir_path, self.outDir)
if __name__ == '__main__':
self.do_update()
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2018 Ondrej Ille <ondrej.ille@gmail.com>
##
## Library with auxiliarly functions for pyXact generator.
##
## Revision history:
## 24.01.2018 First implementation based on the previous stand-alone
## script for generation of VHDL package
##
################################################################################
import argparse
import sys
import time
import importlib.util
import os
import inspect
import math
################################################################################
# File path to the local repo of the PyXact framework
################################################################################
ROOT_PATH = os.path.dirname(os.path.abspath(__file__))
PYXACT_PATH = "./pyXact_generator/ipyxact_parser"
sys.path.insert(0, PYXACT_PATH)
from ipyxact.ipyxact import Component
from license_updater import *
def open_output(output):
return open(output, 'w')
def split_string(input, size):
return [input[start:start+size] for start in range(0, len(input), size)]
def str_arg_to_bool(input):
if (input == "yes" or
input == "true" or
input == "True" or
input == "y"):
return True
else:
return False
def checkIsList(obj):
"""
"""
if (not (type(obj)) == list):
print(str(obj) + " should be a list!")
return false
return True
def checkIsDict(obj):
"""
"""
if (not (type(obj)) == dict):
print(str(obj) + " should be dictionary!")
return False
return True
################################################################################
##
## CAN with Flexible Data-Rate IP Core
##
## Copyright (C) 2018 Ondrej Ille <ondrej.ille@gmail.com>
##
## Base class for specific address Map generators.
## Two separate address maps are considered. Map for address creation
## and map for bitfields, enums and reset values creation.
##
## Revision history:
## 25.01.2018 First implementation
##
################################################################################
from abc import ABCMeta, abstractmethod
import math
class IpXactAddrGenerator(metaclass=ABCMeta):
# IP-XACT memory map object
memMap = None
# Word width (in bits)
wrdWidthBit = None
# Word width in Bytes
wrdWidthByte = None
pyXactComp = None
of = None
def __init__(self, pyXactComp, memMap, wordWidth):
self.wrdWidthBit = wordWidth
self.wrdWidthByte = int(wordWidth / 8)
if (not pyXactComp.memoryMaps):
return None
for map_inst in pyXactComp.memoryMaps.memoryMap:
if map_inst.name == memMap:
self.memMap = map_inst
self.pyXactComp = pyXactComp
def commit_to_file(self, of, text):
"""